STM32 Major LPTIMER documentation shortcoming or is it a silicon design error???

[Kent Swan]

In looking at various LPTIM training documentation it's indicated very clearly that the LPTIMERs have a CNT reset as a function of setting bit 4 of the CR register.

As this is an important capability, there seems to be a number of reference documents documentation follow through problems.

For instance for the RM0410 Reference manual Rev 4 (STM32F76/F77) shows this bit in the register map on page 890/1418 but not in the register detailed description on page 1109/1954 .

In RM0393 Reference manual Rev 2 (STM32L4) the reset bit does not appear in either the detailed register description 886/1418 nor the register map on page 890/1418.

Can any one tell me if this is simply a failure in which sections of STM32 base documentation were copied into processor specific reference manuals or is the LPTIM reset actually missing or flawed on some of these processors. I'm hoping that it's simply a documentation oversight rather than a critical design error in the silicon.

[Bob S]

There are many instances of "copy/paste" or "clone a document and forgot to edit one place" when ST clones reference manuals for a new family of chips. I would place more trust in the features listed in the "LPTIM Implementation" section, as even within a family of chips, some may have this feature and some may not. For example, for the STM32L4xx family, RM0394 (which appears to have replaced RM0393 back in June 2017), version 4, says that only the STM32L41xxx and STM32L42xxx devices have the "reset on read" feature. In the RM0410 (STM32F76/77), the "LPTIM Implementation" section makes no mention of "reset on read". So any appearance in the CR bit descriptions or register map I would tend to treat as edit errors, not an indication that the feature is there.

[Kent Swan]

The LPTIMER documentation indicates the CNT register is read only as opposed to the normal TIMER's CNT register being read/write. In this application we are clocking LPTIM from LSI (the internal 32khz clock). Given that how do you reset the CNT register without a reset functionality?

[Bob S]

Disclaimer: I've never used the LPTimer except to generate periodic wakeup events.

Judging by the STM32L4xxx reference manual, if your CPU doesn't implement the RSTARE and/or COUNTRST bits in the CR, it looks like your only other alternatives to clear the CNT register are to configure the timer for "timeout" function where one of the timer's inputs can clear the counter, or reset the entire LPTIMER peripheral via the RCC.

[Kent Swan]

Can anyone tell me precisely what the LPTIM2_RST peripheral reset bit in APB1 peripheral reset register 2 (RCC_APB1RSTR2) does with respect to a configured LPTIM2

[Bob S]

Try it and find out? 🙂 2 lines of code, one to set the bit in APB1RSTR2 (for LPTIM2) and one to clear it. The use your debugger to read the LPTIM registers.

In general, each RCC peripheral reset signal sets all registers for that peripheral to their "reset" (or power on) state.

[waclawek.jan]

> Can anyone tell me precisely

This is a primarily user-driven forum, with casual ST presence.

The reset bits usually do what they advertise to do: reset all the registers of the given peripheral to the state given in RM as reset state.

Yes, there are many errors in the manuals. You can try to find out experimentally what's the reality; in this particular case it would be quite obvious whether the reset functionality is there or not.

JW

[waclawek.jan]

A quick experiment on the 'L476 DISCO revealed that clearing LPTIM_CR.ENABLE clears LPTIM_CNT too.

I know it's not documented.

JW

[Kent Swan]

Thanks. Experimenting to determine if documented features are present or not and how to devine the mind of both the silicon developer as it relates to missing or inaccurate information is a process I run into all to frequently. Where then do you report suspected or documented manual inaccuracies or need for clarification in a manner that it will eventually end up reviewed and, if appropriate, appear as a correction in a future revisions of those documents? Failing that where can a compendium of 'things-found-out' be located, reviewed and new findings submitted.

[Kent Swan]

Thanks Jan. Actually that kind of makes sense in an undocumented convoluted way because it forces the CNT register to start at a predictable value. Basically a LPTIMx disable/enable is equivalent to an implied reset. I'm going to test this on the L462 that we're using.