We are testing a 300kW inverter prototype, consisting of 12 modules of 25kW, connected in 3 phases of 4 modules in parallel.
Each 25KW module has a full-bridge exit stage of 8 STE88N60M5 transistors, in parallel to 2. The sineworm modulation of the PWM is at 20kHz.
We have discovered an oscillation at 50Mhz in the gates, which we can not eliminate with ferrite toroidals or changing gate resistance values. This oscillation increases in value with the drain voltage, and gets to destroy the transistors.
Attached some images of gate signals and a piece of the schematic.
Could anyone give some help?
