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STM32G0 ADC clock. Max. asynchronous clock according to datasheet is 35 MHz. Is this (35 MHz) the input to PRESC or the output of PRESC ?

JuM
Senior

0690X00000AA0nIQAT.jpg

1 REPLY 1
Hl_st
ST Employee

The ACD clock limitation is behind the divider (in your picture marked as "Or this ?")

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