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SDRAM and adc warnings

_EFrie
Associate III

I am evaluating the STM32F767NIH. I am finding the warnings a bit unclear for the FMC. A brand new project with only the fmc shows a warning triangle that I can't seem to get rid of. I have checked Clock and chip enable SDCKE0+SDNE0, 2 banks, 13 bits, 16 bits, and 16 bit byte enable. I'm sort of clueless with the long list of reasons listed, and it appears this could be par for the course with other screenshots of cubeMX?

Also, I am not understanding the ADC setup. For example, ADC1 IN0 would appear to be a valid choice, it auto selects PAO, which shows as unused in the pinout view. However, this then gives a warning on ETH?

Is there some aspect of pin multiplexing on the STM32 parts that I am not getting?

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