Recognizing SPI data reception in STM32F429

[WKowo]

I'd like to ask how the STM32F429 recognizes data reception in case of SPI while there is no any start bit? I know that there is RXNE bit in SPI_SR status register, but how SPI knows where is the first bit of the transmitted byte? Is it somehow synchronized with SPI data transmission? I mean the first transmitted bit is some kind of trigger for recognizing first received bit (using of course CLK)?

[waclawek.jan · Accepted solution]

If set as master, then it's in the control of clock (SCK). The first bit corresponds to the first transmitted clock.

If set as slave, then it's the first clock after NSS transitions from high to low.

JW

[WKowo]

Thank you for your answer.