SPI problem in STM32F10x

[jerrywalker]

I have a problem with setting up SPI1 in Master mode using the following code. I set the SSM bit to enable software slave management, but when I try to enable the SPI by setting the SPE bit, the MSTR bit is cleared.

Thanks for help.

Jaroslav

RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN | RCC_APB2ENR_SPI1EN;
 
	GPIOA -> CRL &= 0x000FFFFF;
 
	GPIOA -> CRL |= 0xB4B00000;	/// PA7 - MOSI, PA6 - MISO, PA5 - SCK
 
	SPI1->CR1 &= ~SPI_CR1_BR;	// baud rate = fpCLK/2
 
	SPI1->CR1 &= ~SPI_CR1_CPOL;
 
	SPI1->CR1 |= SPI_CR1_CPHA;
 
	SPI1->CR1 &= ~SPI_CR1_DFF;
 
	SPI1->CR1 &= ~SPI_CR1_LSBFIRST;
 
	SPI1->CR1 |= SPI_CR1_SSM;	// software slave management
 
	SPI1->CR1 |= SPI_CR1_MSTR;
 
	SPI1->CR1 |= SPI_CR1_SPE;

[waclawek.jan]

Which STM32?

When you set SSM, the SS input is governed by state of SSI bit - if it's 0, it's the same as if you'd not set SSM and pulled the NSS pin low, i.e. it switches to slave mode.

JW

PS. A stylistic one: I prefer to set peripheral registers all at once, in a single write, instead of a series of RMW operations.

[jerrywalker]

Thank you.