STM32G071RB Nucleo board - Cannot write to TIM3->EGR

[JuM]

Cannot write to TIM3->EGR, Writes to EGR are stored in SR.

stm32g071xx.h definitions are correct.

Assembler output also shows correct addresses and offsets.

;;;1157      TIM3->DIER |= TIM_DIER_UIE;

0000b8 4608             MOV     r0,r1

0000ba 68c0             LDR     r0,[r0,#0xc]

0000bc 2101             MOVS    r1,#1

0000be 4308             ORRS    r0,r0,r1

0000c0 4922             LDR     r1,|L20.332|

0000c2 60c8             STR     r0,[r1,#0xc]

;;;1158      TIM3->SR  |= TIM_SR_UIF;             

0000c4 4608             MOV     r0,r1

0000c6 6900             LDR     r0,[r0,#0x10]

0000c8 2101             MOVS    r1,#1

0000ca 4308             ORRS    r0,r0,r1

0000cc 491f             LDR     r1,|L20.332|

0000ce 6108             STR     r0,[r1,#0x10]

;;;1159      TIM3->EGR |= TIM_EGR_UG;

0000d0 4608             MOV     r0,r1

0000d2 6940             LDR     r0,[r0,#0x14]

0000d4 2101             MOVS    r1,#1

0000d6 4308             ORRS    r0,r0,r1

0000d8 491c             LDR     r1,|L20.332|

0000da 6148             STR     r0,[r1,#0x14]

;;;1160      TIM3->CCMR1 |= TIM_CCMR1_CC1S;

0000dc 4608             MOV     r0,r1

0000de 6980             LDR     r0,[r0,#0x18]

0000e0 2103             MOVS    r1,#3

0000e2 4308             ORRS    r0,r0,r1

0000e4 4919             LDR     r1,|L20.332|

0000e6 6188             STR     r0,[r1,#0x18]

​                 |L20.332|

                         DCD     0x40000400

But memory shows this.

Writes to DIER and CCMR1 are stored ok.

Writes to SR have no effect, nothing stored.

Writes to EGR are stored in SR.

 0x40000400: 80 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 03 00 00 00

//                      CR1               CR2               SMCR           SR                EGR               CCMR1

Bug in STM32G071RB ?

Errata sheet has no matching issue...

Best regard

Juergen

[Uwe Bonnes]

TIM->EGR is write only. Writes 1 to some EGR register triggers some event. So how do you find out that writes to EGR do not succeed?

[JuM]

​Aaah, thank you for making this clear and sorry for my misunderstanding.

The write to EGR.UG generates the event and as  follow up SR.UIF shows that this event is now pending.

Best regards

Juergen

[JuM]

Wondering of SR.UIF set, as timer is still disabled.

So counter should not overflow.

My TIM3 setup is as this:

   TIM3->ARR  = (SystemCoreClock / CurrentSampleRate) - 1;

   TIM3->CR1 |= TIM_CR1_ARPE;                                   // ARR buffered

   TIM3->EGR |= TIM_EGR_UG;                                      // Force update generation (UG = 1)

After this, SR.UIF is set to 1...

   TIM3->CNT  = 0xFFFFFFFF;                                      // let first interrupt immediately occur to immediately start ADC conversion

   TIM3->CR2 |= (TIM_CR2_MMS_1);                                 // Update event of timer will trigger TRGO​