How do I set complimentary timer outputs in PWM mode to the same final state?

[Michael98006]

Is there a way to run N PWM cycles on TIM_CH1 and TIM1_CH1N (complimentary outputs of CH1) in OPM and set the final state of both outputs to low at the end of the final PWM cycle?

I'm using TIM1 in slave configuration with slave mode set to combined reset trigger mode with PWM mode 1 selected. My issue is that I end up with one of the two outputs set "high" when I want them both to be "low" at the end of the last PWM cycle.

[waclawek.jan · Accepted solution]

I don't think you can do it purely in hardware, but after the cycle ends, you can change the CHxN polarity by changing the respective CCxNP bit in TIMx_CCER. These bits are preloaded, if TIMx_CR2.CCPC is set, so you can write TIMx_CCER in advance before the last update event, and it will come into effect at the update event.

JW

[Michael98006]

I liked the idea of turning outputs on/off "by hand", but I went a step further and toggled the MOE bit on in the update event interrupt before the first PWM pulse and clearing the MOE bit on the update interrupt from the end of the last PWM cycle.