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Disable DMA on SD card, FIFO empty, non-zero SD FIFOCNT, DBKEND not set, SD block offset each write.

ZThat
Senior

Hello,

I am having issues with using the DMA to transfer SD card data to RAM. This may have to do with my configuration settings, because the FIFO error register is automatically set when I configure the SD card DPSM (not when I enable the DMA configuring the DPSM happens after enabling the DMA in the HAL).

I get small transfers to work just fine, but larger transfers that almost fill the DMA 16 bit counter are causing issues. It seems as thought the SD card is offsetting the data being transferred after my first few transfers. This offset only happens once, and then is consistently wrong. It seems as if the destination on the SD card is correct, but it is pulling from the wrong memory address. Even though I check that the memory address that I insert into this writeblocks function is the same every time.

I should say that the DBKEND bit is being set in my smaller transfers, but not the larger transfers. My smaller transfers also don't require that I poll for the SD card status because the transfer is complete when I receive the SDMMC dataend interrupt.

All the Best,

Zach

1 ACCEPTED SOLUTION

Accepted Solutions
ZThat
Senior

I figured this out. I was interleaving DMA transfers and IT transfers. The IT transfers must have been reconfiguring the SDMMC in such a way that the transfer ready signal was not a valid way to ensure that it was actually ready for another DMA transfer.

As a side note, it is very important when using the DMA for large information transfers to the SD card to actually poll the SD card status with formal SD commands. The dataend interrupt does not necessarily mean that the data transfer is complete.

Another important thing to mention is that the DMA's 16 bit counting register counts every single beat when in burst mode. So the maximum amount of data that can be send in one "writeblocks" is 4 bytes (1 word) X 65,536 = 262144 bytes. Transfers larger than that need to be broken up.

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1 REPLY 1
ZThat
Senior

I figured this out. I was interleaving DMA transfers and IT transfers. The IT transfers must have been reconfiguring the SDMMC in such a way that the transfer ready signal was not a valid way to ensure that it was actually ready for another DMA transfer.

As a side note, it is very important when using the DMA for large information transfers to the SD card to actually poll the SD card status with formal SD commands. The dataend interrupt does not necessarily mean that the data transfer is complete.

Another important thing to mention is that the DMA's 16 bit counting register counts every single beat when in burst mode. So the maximum amount of data that can be send in one "writeblocks" is 4 bytes (1 word) X 65,536 = 262144 bytes. Transfers larger than that need to be broken up.