Forcing timer output state in gated PWM mode when gate goes low?

[Yoichi Shinoda]

When generating a series of pulses in PWM mode with the series duration controlled by gated slave mode, final state of output depends on the timing the gate signal goes down.

Is there anyway to force the state to low, so that the final pulse is not stretched? Short pulse is okay.

[waclawek.jan · Accepted solution]

You did not tell us which STM32 and whcih timer, but generally I don't think there is a simple way to accomplish what you want. Some timers have the option to clear OCxREF upon external event but that's driven usually by the ETR pin, and not many timers have that pin, besides, you would need to externally link the trigger source to ETR, wasting pins (unless ETR is the source of TRGI now, of course).

Other option which comes to my mind is to set up a DMA triggered by TIMx_DIER.TDE, transferring a suitable value (0?) from memory to TIMx_CNT so that the OCxREF comparison results in inactive state.

JW

[Yoichi Shinoda]

Thanks for the ideas. I understand that there's no easy and generic way.