stm32h7 nucleo clock setting

[Bilge]

I use stm32h7 nucleo board and there is gpio example in stm32cubeh7 and I changed clock configuration ,but it doesn't work.STM32CUBEh7-project-nucleo-example-gpio-gpio ext

static void SystemClock_Config(void)
{
  
 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
	
 
	
  /*!< Supply configuration update enable */
  MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);
 
  /* The voltage scaling allows optimizing the power consumption when the device is
     clocked below the maximum system frequency, to update the voltage scaling value
     regarding system frequency refer to product datasheet.  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
  
  
  /* Enable HSE Oscillator and activate PLL with HSE as source */
  RCC->CR |=  RCC_CR_HSEON;  // HSE yi etkinlestir
	//HSE hazir olana kadar bekleyin ve Zaman asimina ulasildiysa çikin.
		
 do
  {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;  //HSE clock ready flag
    StartUpCounter++;
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 
  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  {
    HSEStatus = (uint32_t)0x01;
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
  }
 
  if (HSEStatus == (uint32_t)0x01)
  {
    /*  set Flash Latency */
    FLASH->ACR = (uint32_t)FLASH_LATENCY_4;
 
		/*HCLK*/
  RCC->D1CFGR |= RCC_HCLK_DIV2 ;
	
	/*D1PCLK1*/
	RCC->D1CFGR |= RCC_APB3_DIV2 ;
			
	/*D3PCLK1*/
	RCC->D3CFGR |= RCC_APB4_DIV2; 
	
	/*PCLK1*/
	RCC->D2CFGR |=RCC_APB1_DIV2;
	
	/*PCLK2*/
	RCC->D2CFGR |= RCC_APB2_DIV2;
		
		
		
		/*pll kaynagi olarak  HSE seçilir */
		RCC->PLLCKSELR |= (( uint32_t )RCC_PLLCKSELR_PLLSRC_HSE );   //PLLs Clock Source Selection Register
		/* PLL1 kullanilmadiginda güç tasarrufu saglamak için DIVM1'in degeri ‘0’ olarak ayarlanmalidir. */
		RCC->PLLCKSELR |= (( uint32_t ) RCC_PLLCKSELR_DIVM1_0); //Prescaler: /1
		
		/*RCC PLL1 VCO Range Wide VCO range: 192 to 836 MHz*/
  	RCC->PLLCFGR |= RCC_PLL1VCOWIDE ;
		
		/* PLL1 input frequency Range 4-8mHz */
		RCC->PLLCFGR |= (( uint32_t )RCC_PLLCFGR_PLL1RGE_2 );
		
		/*Enable clock output*/
		RCC->PLLCFGR |= RCC_PLLCFGR_DIVP1EN ;
		
		/* Multiply by 100 DIVN1*/
		CLEAR_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1_Msk);
    SET_BIT(RCC->PLL1DIVR, 0x63);
		
		/* Divides by 2 by default */
		/* Enable PLL */
    RCC->CR |= RCC_CR_PLLON;
		     
    /* Wait till PLL is ready */
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
    {
    }
		
     /* Set System Clock to PLL */
		CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
    SET_BIT(RCC->CFGR, RCC_CFGR_SW_PLL1);
      
    /* Wait till PLL is used as system clock source */
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SW_PLL1)
    {
    }
  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock
         configuration. User can add here some code to deal with this error */
		Error_Handler();
  }
}