Please explain DMA requests for multiple timer channels on the same stream

[TDK]

On an STM32F4, I am using a timer in IC mode using a DMA transfer. I'm able to do this by setting up and using HAL_TIM_IC_Start_DMA. For a given timer channel, the "DMA request mapping" table in the datasheet shows which stream is connected to which timer. For example, DMA2 stream 1 is connected to TIM1_CH1 on channel 6.

Interestingly, for DMA2 Stream 6 channel 0, the datasheet says it's connected to TIM1_CH1, TIM1_CH2, and TIM1_CH3. What does this mean exactly? Will it trigger a DMA transfer when any one of those three channels has an event? Am I right in assuming there is no way to know which channel triggered the DMA transfer?

[TDK]

To answer my own question here, DMA2 stream 6 channel 0 can be configured for any one of channels 1, 2, or 3. This is done in HAL_TIM_IC_Start_DMA. It cannot be enabled for multiple channels at the same time. This is evident in the call to HAL_DMA_Start_IT where it gives the source address as the CCRx register for the relevant timer channel.

[waclawek.jan]

Cube/HAL's design choices have nothing to do with the real physical implementation of the given peripheral. Moreover, timer-triggered DMA transfers don't necessarily have TIM registers as source or destination.

> What does this mean exactly? Will it trigger a DMA transfer when any one of those three channels has an event? 

Yes, if all three (or any two of them) are enabled to trigger DMA in TIMx_DIER.

> Am I right in assuming there is no way to know which channel triggered the DMA transfer?

Yes.

JW