SPI: delay between write to TXDR and start of clock

[Mr_M_from_G]

Hello ,

With SPI (SPI2 in my case) I experience a delay between a wite to TXDR and the start of the SCK activity in case of an empty TX fifo. It seems to be something like 5 SCK periods, so it changes with SCK frequency but this ratio remains. I checked with several values of MBR. The ratio is a little smaller for higher frequencies ie the delay is shorter in terms of SCK periods.

This effect is largest at the first transmission after enabling SPI and reduces to a ratio of about 3 for subsequent transmissions, but only if TX fifo is empty when TXDR is written.

Sending back to back and inserting some delay with MIDI works fine when I write several values to TXDR in a row.

(My findings after some experiments)

Any idea why that is and how to get rid of it?

Thanks a lot

Martin

[Mr_M_from_G]

Some more information:

frequent repeats of writing to TXDR results in delay times between 3.25 and 4.25 SCK cycles, measured at 417 kHz.