Always getting SPI OVR Error instead of executing SPI RX callback functions while interfacing SPI1 + DMA + STM32H7

[nirav soni]

For DMA, allocating the buffer to the right memory segment,

I am already allocating the buffer in to D2 (0x30000000), which I think should be right, and I haven't enabled the cache yet, for remaining all nonvolatile memory allocated in section D1 (0x240000000).

Figure-1 updated STM32H743ZITx_FLASH.ld

Figure-2 Used SPI configuration in cubeMX:

Figure-3: Used DMA configuration in cubeMX:

In program Switching SPI mode in to Receive only master mode,

Initiating DMA process by calling function (see Figure-4)

Figure-4

Observed DMA generates interrupts two times, one when half of the buffer is received and another one when the second half is received (whole).

Expecting following function to be called (see Figure-5)

But always getting SPI_ERROR_OVR (see Figure-6)

Figure-6

This will eventually calls HAL_SPI_ErrorCallback(hspi) and return instead of HAL_SPI_RxCpltCallback(hspi)

Figure-7

Same experiment works well with STM32F7 but always getting OVER RUN Error in STM32H7.

Means Configuring SPI peripheral to SPI1, using DMA1 and reading data in normal mode, eventually generates the both HT & CT interrupts for DMA, but in CT it always generates the SPI OVER RUN error instead of calling

HAL_SPI_RxCpltCallback(hspi)

How to resolve this issue, Guys please help.

[Tesla DeLorean]

Please don't ping me privately about posts on the forum.

I can't help you with CubeMX/HAL defects.

Make sure the buffer is in fact at the address ranges expected. Check what status/errors the DMA unit is reporting.

Check the lengths or transfer units are consistent.

If the DMA is placed in circular mode does it cause errors then? If not points to inconsistent size expectations in transfer.

Check appropriateness of FIFO settings.

Check for off-by-one issues of TX vs RX