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RM Error (IWDG Debug Mode)

flyer31
Senior

In the RefMan 44.3.8 (June 2018) it says "... depending on DBG_IWDG_STOP configuration bit..." , but this seems to be some STM32F4 remainder ... I think it should better say "...DBGMCU_APB4FZ1_WDGLSD1 configuration bit...".

2 REPLIES 2
Khouloud GARSI
Lead II

Hi @flyer31​ ,

I have reported your feedback internally and a fix will be added to the next release of the reference manual.

Thank you for bringing this to our attention!

Khouloud.

Khouloud GARSI
Lead II

Hi @flyer31​ ,

The RM is now updated as follow:

...  depending on the configuration of the corresponding bit in DBGMCU freeze register. 

Thanks again for your feedback!

Khouloud.