Replacing HW by SW has limits, If the TX of your "USART" are not sending simultaneously, you could share a HW USART by changing which GPIO will become the "TX" pin. This will relax a bit the core.
Worst case is all SW UART receive a start bit at once. SW will queue these interrupts and create latency. When it exceed one UART bit duration, the system will fall apart. Cranking the SYSCLK up, putting the EXTI interrupts in SRAM (and its vectors) might help a bit.
Another issue will be that in the end there won't be enough DMA streams for all these UART needs.
