what is the sampling time in ADC ?

[MNapi]

I am using STM32F446 and I see 15 cycles for 12 bit ADC which gives 1.5 Msps for 180 Mhz clock

But I see on the bottom sampling time from 3 cycles to 480 cycles under something called rank.

does it means that it would actualy do one sample in 3 cycles which would give 7.5 Msps which is more than the maximum speed in data sheet,

[raptorhal2]

No.

The sampling time is the ADC clock cycles for which the sample and hold capacitor is charged up to the channel input voltage. The ADC then requires another 12 clock cycles to convert to 12 bits accuracy.

The programmable range in sampling time is needed to accommodate a range if input signal impedance, since higher input impedance take longer to charge up the capacitor.

Cheers, Hal

[MNapi]

But the math does not make sense it would mean then that it is 15 cycles + 3 cycles. The clock driving ADC is 22.5 Mhz (the board clock is 180 Mhz)

And it does 1.5 Msps for 12 resolution which corresponds to 15 clock cycles not 18

For 6 bit resolution it is 9 clock cycles which is 2.5 Msps. And it is the bard data saying fastest speed is indeed 2.5 Msps

[S.Ma]

I guess it's time for CubeMX to give usec units of the ADC timings to help everyone.

[Tesla DeLorean]

fADC = 30 MHz (typ) 36 MHz (max)

The conversion time takes 12 cycle, min sample time 3 cycles (12 + 3)

12-bit resolution single ADC

30/15 = 2 Msps

12-bit interleaving (two ADC, where 3-12 cycles of sample time can be hidden, conversion time limits)

30/12 = 2.5 Msps

In a triple interleave mode you get 3 samples every 12 cycles, ie saturates at 4 cycles, and 3 cycle sample hidden

30/12 * 3 = 7.5 Msps