The reason I need this information is because I would like to use the two internal 'half-bridge' of the STGAP2D gate driver for directly driving a resistive load at ~ 300 mA (more explanation below). In addition, the configuration / topology I am targeting is special since I would have the GNDISO_A and _B tied together to a constant current sink circuit (and not to ground) so that the internal GOFF NMOS devices operate (somehow) as a differential pair.
- A first question is does an ST designer see a problem with the 'current driven' topology I am describing above.
- If not, and assuming the current sink I am tying to GNDISO_A/B is ideal, I would like to know the voltage I would obtain at GNDISO_A/B if the current sink is e.g. 300 mA going into one of the two GOFF MOS and whether this voltage depends on VH_A = VH_B supply (I target VH_A = VH_B = 26V).
- I am expecting GNDISO_A/B voltage to be VG_INT - VGS where VG_INT is the on-chip voltage applied to the gate of GOFF NMOS devices and VGS is their gate-source voltage drop for 300 mA. The voltage at GNDISO_A/B in the above conditions will tell me the voltage headroom I need for my current sink, since it is eventually not ideal.
- A last electrical characteristic I would need is the typical leakage current of the drain-source GOFF NMOS bulk diode in the above conditions (1) between 70°C and 125°C.
(1) VH_A = VH_B = 26V, GNDISO_A/B = answer to previous question for drain current = 300 mA
