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Is there a possible bug in function HAL_SPI_Transmit_DMA() (STM32Cube_FW_H7_V1.3.0)?

ddl22
Associate

Hi everyone!

I'm trying to transmit some data using SPI2 on a NUCLEO-H743ZI board (only TX). To do it fast I'm using DMA with HAL_SPI_Transmit_DMA(), but it returns with an error (from line 1465 in stm32h7xx_hal_spi.c):

/* Packing mode management is enabled by the DMA settings */
  if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))    || \
      ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
                                                         (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
  {
    /* Restriction the DMA data received is not allowed in this mode */
    errorcode = HAL_ERROR;
    __HAL_UNLOCK(hspi);
    return errorcode;
  }

After replacing 'hdmarx' to 'hdmatx' (as I'm only trying to transmit some data and I'm not interested in receiving) it works as it supposed to.

Is this a possible bug, or am I just lucky to make it work somehow (I'm new to HAL)?

13 REPLIES 13
Amel NASRI
ST Employee

Hello @Balázs Ölvedi​ ,

As you are using SPI in transmission mode, you need to configure SPI Tx DMA Handle parameters.

You are right, this is an error in the driver that I'll report internally.

-Amel

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

ddl22
Associate

Also found a typo in stm32h7xx_hal_spi.h at line 699:

//Line 687:
/** @brief  Clear the SPI UDR pending flag.
  * @param  __HANDLE__: specifies the SPI Handle.
  * @retval None
  */
#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
 
 
//Line 699:
/** @brief  Clear the SPI UDR pending flag.
  * @param  __HANDLE__: specifies the SPI Handle.
  * @retval None
  */
#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)

I'm guessing the comment should say: "Clear the SPI TXTF pending flag".

Amel NASRI
ST Employee

Thanks for sharing your finding. We will take care to fix it.

-Amel

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

I am doing the same thing (STM32H743, SPI DMA transfer) except I am using transmit and receive (Master mode, full duplex).  I have set both tx buffer and rx buffer as 32 byte aligned.  My code is falling out at the same place, but now it is at line 2324 :

 

/* Restriction the DMA data received is not allowed in this mode */

errorcode = HAL_ERROR;

I notice that the check is still being made with respect to hspi->hdmarx.

So is this still a bug? I tried pointing to ->hdmatx but that does change the error.

I went back to my original test bench for this code which used a STM32G0xx and an Arty-7 board, testing spi communication between STM32 and Xilinx Series 7 FPGA.  It works fine using Full-Duplex DMA.  The STM32G0xx HAL code for  HAL_SPI_TransmitReceive_DMA() is very different and the alignment checks are performed in a more broken out manner with checks made with multiple if statements depending on the SPI mode in use.

 

In a previous reply, you stated, "As you are using SPI in transmission mode, you need to configure SPI Tx DMA Handle parameters."

Care to share what all the entails?  Only in my case I am full duplex.  Are the SPI Tx and Rx DMA Handle Parameters handled in CubeMX or after?  Details are needed.

So it appears that the information in the Handle structure for the hspi is not getting intialized in the area of

hspi->hdmarx.Init.MemDataAlignment.  Currently, when the call to HAL_TransmitReceive_DMA is made, this value is 0 and the code expects it to be either 16384 or 8192 (WORD or HALFWORD aligned).    

I tried changing the hdmarx and hdmartx values in the MX_SPI5_Init() call and this fixes the problem.

I found that the the HAL_SPI_Init() call includes a call to HAL_SPI_MspInit() and in there the hdma[rt]x values are hard coded to by Byte Aligned and nothing is done to provide for other alignments.

 

Sorry, forgot to include the details:

In the MX_SPI5_Init() call, (which SPI5  is set for 16 bit transfer in CubeMX) in the user section I put:

/* USER CODE BEGIN SPI5_Init 2 */

hspi5.hdmarx->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;

hspi5.hdmatx->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;

/* USER CODE END SPI5_Init 2 */