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L6591 documentation issue regarding PWM nature

RMari
Associate II

The datasheet notifies the the exact 50% Duty limitation because of using a T-flopflop that divides the oscillator frequency by two. Figure 48 (Oscillator waveforms and their relationship with gate-driving signals) suggests that each output would be narrower when the regulation loop requires it (both outputs OFF). The block diagram suggests this, too by apparently hiding the T-flipflop in the "dead time adjustment & logic" block.

On the other hand, the text clearly states D resp. 1-D (which is - BTW - the only way to get ZVS).

The ambiguity was resolved after reading the 90W design note. The oscillograms here clearly document the D resp. 1-D nature.

I'd suggest to modifiy Figure 48 such that it is clearly stated that this figure represents the open loop condition and that only the even pulses trigger a switch action (LGoff-dt-HGon), and the reverse action is due to a control loop response OR an odd pulse, whatever comes first. The description on top of page 29 can be overlooked too quickly during a query whether the IC fits an application or not.

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