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STM32F103C8 - NRF24L01+ Flush and Read Payload Commands Do not Work

STM32F103
Associate

Hi,

I use a STM32F103 as a receiver and an Arduino Uno as a transmitter.

I continuously read FIFO_STATUS and STATUS registers. Before I turn transmitter on, everything is okay. Registers tell me that there is no data in RX FIFO. Once I turn the transmitter device on RX_DR bit in STATUS register is set high and FIFO_STATUS register says that there is data in RX FIFO and FIFO is full. Although I execute Flush command, nothing changes.

FIFO_STATUS register still says that there is data in FIFO and FIFO is full.

void Flush_RX()
{
  csn_low();
  HAL_SPI_Transmit(&hspi1, (uint8_t *)COMD_FLUSH_RX,1, 150);
  while( (HAL_SPI_GetState(&hspi1) != HAL_SPI_STATE_READY) ){}
  csn_high();
}

I have got a similar problem with READ_RX_PAYLOAD command. When IRQ pin goes low and RX_DR bit is set high, I execute the command but what I read is the content of STATUS register. I cannot read data that has been sent from TX.

void ReadPayload()
{
HAL_Delay(1);
csn_low(); //CSN=0
HAL_SPI_TransmitReceive(&hspi1, (uint8_t *)COMD_R_RX_PAYLOAD, &received_data, 1,150);
while(HAL_SPI_GetState(&hspi1) != HAL_SPI_STATE_READY);
CDC_Transmit_FS(&received_data,1); // print the received data out
csn_high(); // CSN=1
HAL_Delay(1);
}

Then I made some changes on code. 

I send READ_RX_PAYLOAD command through SPI and then send NOP command. This time I receive 0x00.

I've just checked R_RX_PL_WID command and there is the same situation.

I want to ask one more question. Below the command list section in datasheet, it says "When accessing multi-byte registers read or write to the MSBit of LSByte first."

The word for FLUSH_RX is 1110 0010 that is 0xE2. When I send this command through spi, should I send just 0xE2 or in reverse order (0x2E). 

I can write to registers and read registers very well. There is no problem.

I am confused.

Any suggestion, help, guidance will be appreciated. Thanks in advance.

1 REPLY 1
Susano
Associate II

better late than never I have the same problem just now

if you are sure the SPI configuration is working well then you should note that you need a delay of at least 2ns before setting the CS pin high again.

mentioned in the datasheet section 8.3.2 SPI timing