Problem in reading 512kB data over FSMC with 8bit Asynchronous Muxed NOR configuration.

[Pranay Dhuri]

Hi there,

I have configured ST32F207VGT for FSMC asynchronous muxed NOR configuration, FPGA is connected to the bus at other end.

Following is the FSMC configuration done on MCU

 hnor1.Instance = FSMC_NORSRAM_DEVICE;

 hnor1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;

 /* hnor1.Init */

 hnor1.Init.NSBank = FSMC_NORSRAM_BANK1;

 hnor1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_ENABLE;

 hnor1.Init.MemoryType = FSMC_MEMORY_TYPE_NOR;

 hnor1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8;

 hnor1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;

 hnor1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;

 hnor1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;

 hnor1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;

 hnor1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;

 hnor1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;

 hnor1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;

 hnor1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_ENABLE;

 hnor1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;

 /* Timing */

 Timing.AddressSetupTime = 5;

 Timing.AddressHoldTime = 5;

 Timing.DataSetupTime = 10;

 Timing.BusTurnAroundDuration = 10;

 Timing.CLKDivision = 0;

 Timing.DataLatency = 0;

 Timing.AccessMode = FSMC_ACCESS_MODE_A;

MCU is configured to operate at 120MHz.

We are reading 4 bytes of data over FSMC and sending the same over USB. This procedure we are repeating for 512k times in order to receive and send 2MB of data .

We are able to read nearly 4000Bytes data correctly, data received after that is not proper or zeros (may be sync problem)

Data= *(__IO uint8_t*) (0x60000000 + 0x00 + 0x00);

Above is used to get data from FPGA.

Need suggestions to resolve this sync problem and get product ready.

[waclawek.jan]

What makes you believe that the problem is at the STM32 end? Do you observe the data on the buses?

JW

[Tesla DeLorean]

You're going to need to hook up a logic analyzer to view what is actually occuring, and perhaps have the STM32 trigger when it observes an anomaly from its end.

Once you understand the problem you might be able to alter settings, or alter the behaviour of the FPGA to match the expectations of the host.