Bad clock settings for an STR9

michael · ‎2008-04-13

Posted on April 14, 2008 at 07:32

michael · ‎2011-05-17

Posted on May 17, 2011 at 09:51

Hello all,

I have just recovered my STR9 from a fatal startup crash due to invalid setting of the SCU_CLKCNTR. My PLL generates a 48 MHz clock, and the source of the problem was the APBDIV bit field: dividing RCLK (=48 MHz) by 2 (so that APB is fed by a 24 MHz clock) is presumably invalid. But why is that? I have re-read the clocks chapter in the reference guide, to no avail.

michael · ‎2011-05-17

Posted on May 17, 2011 at 09:51

for those of you who don't care... :), if you try to run a STR9 at 48 or 96 MHz, must set the FMISEL bit in SCU_CLKCNTR to slow don't the flash. The simulator does not complain about it, even the hardware does not work (and you must perform a manual flash erase procedure, ouch...)

amira1 · ‎2011-05-17

Posted on May 17, 2011 at 09:51

Hello michael.tamir,

I didn't understand very well your problem. But I think you are talking about the system reset at 96MHz limitation.

What is the silicon version you are using? If you are working with STR91xF(rev D), please refer to the errata sheet(the system reset at 96MHz section). This limitation is already fixed in the new silicon version.

Could you please explain more if it is not really the problem that I explain.

Best regards,

mirou.

michael · ‎2011-05-17

Posted on May 17, 2011 at 09:51

mirou,

thanks for your reply. see a newer thread:

http://www.st.com/mcu/forums-cat-6694-21.html

I am working with a STR912FW44X, I am not sure what revision (B or D). I have experienced problems with th device operating at 48 MHz: It seems that cetain PCLK divides did not allow the device to start up correctly (I think that any divider did render the device unusable until I performed a manual flash erase procedure) unless the flash clock is slowed. Generally, are there any divider combinations that are not allowed?