Posted on March 27, 2008 at 06:07Hello,
I am new to the STR7 and I was hoping you'd be able to clarify something simple for me: I have configured my processor with the following code:
Code:
<BR> RCCU_MCLKConfig(RCCU_DEFAULT); // MCLK = RCLK <BR> RCCU_FCLKConfig(RCCU_RCLK_2); // FCLK = RCLK/2 <BR> RCCU_PCLKConfig(RCCU_RCLK_4); // PCLK = RCLK/4 <BR> RCCU_PLL1Config(RCCU_PLL1_Mul_12, RCCU_Div_2); // 48MHz PLL @ 16MHz XTAL <BR>
Now I have read the data sheet, but I don't understand how the period of my TIM3 is calculated to be ~10[ms] with the prescaler 1, when it is fed by PCLK2 (whose speed is 12 MHz). I also don't understand why CNTR input frequency is 6000 kHz. Could you please clarify HOW the 12 MHz input clock ends up as a 10[ms] period of TIM3? I calculated all these numbers with STR71x_Calculation.xls.
Thanks in advance!
[ This message was edited by: michael.tamir on 27-03-2008 10:38 ]
