FSMC_NEx

[lonnie]

Posted on November 27, 2009 at 20:04

FSMC_NEx

[lonnie]

Posted on May 17, 2011 at 13:31

Does anyone know if the FSMC has a parameter that can directly modify the amount of time that a chip select line (NEx) will be held high in between two consecutive write operations?

I have a nonmultiplexed asynchronous 16bit external SRAM device connected to the FSMC (Bank1) operating in access mode A. My address setup time is 0 and my data setup time is 5, so the total time my chip select line will be held low, during a write operation, is (1 (ADDSET + 1) + 6 (DATAST + 1) * 13.8 (tHCLK)) 96.6ns. I verified via scoping the NEx pin that the chip select is low for ~96.6ns during a write operation to external SRAM, but when I perform a consecutive write to SRAM it takes 6 tHCLK cycles before the chip select line goes low again. Can someone explain why it takes 6 clock cycles for bus turnaround and can it be modified? Thanks Lonnie [ This message was edited by: lonnie.walker on 25-11-2009 18:11 ]

[gahelton12]

Posted on May 17, 2011 at 13:31

The ''Busturn'' parameter allows you to set this time (to some extent). In RM0008, look at note 1 below the timing diagram on page 429. It says that setting Busturn below 5 cycles has no effect for back to back transactions. This seems like a significant penalty for external memory access. But I would expect that this would be improved for next generation devices.

[lonnie]

Posted on May 17, 2011 at 13:31

Thanks gahelton1 for the reply.

I'm operating in access modeA, so the busturn parameter has no affect in my case. However as you have mentioned, setting the busturn around less than 5 has no affect in the timing mode on page 429. This is due, according to the note, to the ''delay between side-by-side transactions'' and busturn being equal for <= 6tHCLKs. It therefore seems that NEx will always be high for at a minimum of 6tHCLKs (@72Mhz = ~82ns) between consecutive transactions.