Posted on September 24, 2013 at 09:22> Depends on the PHY. The LAN8720 can take a 25 MHz source.
Yes, but the venerable DP83848C which is used on the STM3240G-EVAL board is not of that kind.
> To get 50 MHz out of MCO (PA8) you'd need to run the processor at a multiple of 50 MHz (ie 150 MHz for the F4),
> you could perhaps also use PLLI2S and MCO2 to get 50 MHz independently of the CPU clock if you didn't care for I2S.
I would be wary of the usage of PLLs inside a SoC for this purpose. While the datasheet specifies ''some'' jitter for PLL as ''Main clock output (MCO) for RMII Ethernet'', it does not say what are the conditions for this (namely used crystal and PLL settings, or any other if applicable), specifies it as ''cycle to cycle at 50MHz on 1000 samples'' as 32ps which is most probably RMS and not peak-to-peak nor cumulative; and it's a typ not a max. I'd also expect some coupling between the digital functions and the PLL. There's also an alarming footnote, saying ''the use of 2 PLLs in parallel could degraded (sic) the jitter up to +30%. All in all, even if the PHY's documentation (AN-1548) claims workability up to 4ns jitter and its datasheet guarantees working with 800ps jitter, I personally go for an ''extra'' oscillator, rather than potential stability/reliability problems. YMMV.
Another option is to feed the STM32's clock input from the same oscillator (if it supports the load); or go for some of the modern PHYs working out of 25MHz (and supporting a 25MHz crystal, too), as Clive suggested above. The EVAL board is unusable in this respect, but there are 3-rd party devboards out there featuring such PHY.
JW
