STM32F4Discovery - DMA not work.

[alprof]

Posted on July 31, 2013 at 20:14

I did try send 100 words 16bits from memory to memory by DMA, and it not work.

uint16_t bufor_od[100];

 uint16_t bufor_do[100];

 RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;

 DMA_InitTypeDef DMA_InitStructure;

 DMA_DeInit(DMA1_Stream0);

 DMA_InitStructure.DMA_Channel = DMA_Channel_0;

 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)bufor_od;  DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)bufor_do;  DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToMemory;  DMA_InitStructure.DMA_BufferSize = (uint32_t)sizeof(bufor_od)/2;  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;  DMA_InitStructure.DMA_Priority = DMA_Priority_High;  DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;  DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;  DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;  DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;  DMA_Init(DMA1_Stream0, &DMA_InitStructure);

 DMA1_Stream0->CR |= (uint32_t)DMA_SxCR_EN;

#rtfm

[Tesla DeLorean]

Posted on July 31, 2013 at 21:01

''�? Each stream also supports software trigger for memory-to-memory transfers (only available for the DMA2 controller)''

''1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 controller, thus only DMA2 streams are able to perform memory-to-memory transfers.''''Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral. This is the memory-to-memory mode, described in Figure 30. When the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the stream immediately starts to fill the FIFO up to the threshold level. When the threshold level is reached, the FIFO contents are drained and stored into the destination. The transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the DMA_SxCR register is cleared by software. The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register. Note: When memory-to-memory mode is used, the Circular and direct modes are not allowed. Only the DMA2 controller is able to perform memory-to-memory transfers.''

[alprof]

Posted on July 31, 2013 at 21:15

Yes, now work:) Thank you! I read English slow and it is for me very hard to read whole documentation, however everything is in documentation. Thank you so much.