GPIO switch from input to output time with STM32F103

bikejog · ‎2013-09-04

Posted on September 04, 2013 at 17:19

Hi there,

If PortD is originally configured as input and then the following code is executed, how long will it take 0x5AA5 to appear on portD after the ->CRL assignment completes? Can't seem to find this in the datasheet. Since output is set for 10 mHz, the voltage should appear within 100 nSecs? But is there any delay when switch from input to output?

GPIOD->ODR = 0x5AA5;

GPIOD->CRH = 0x11111111;

GPIOD->CRL = 0x11111111;

TIA

Andy

#gpio

John F. · ‎2013-09-05

Posted on September 05, 2013 at 09:51

The output ''speed'' setting just controls the slew rate of the output driver - so you can choose slower rates for decreased power consumption and less electrical noise etc. There will be a delay between the processor core handling the instruction and the GPIO output changing that is caused by the time taken for the signal to traverse the peripheral bus structure and bridges : AHB-APB2-GPIO on the STM32F103. If you need sub-microsecond accurately timed fast pulses, you may need to use external electronics hardware.

dthedens23 · ‎2013-09-05

Posted on September 05, 2013 at 19:20

There may be a delay. Check the data sheet. The core is clocked at a frequency, but peripherals are often clocked at some slower speed. And, as John says, it has to travers the bus/bridge.

bikejog · ‎2013-09-05

Posted on September 05, 2013 at 22:31

>> There may be a delay. Check the data sheet.

Is this delay you refer to the time it takes to write to the CRH and CRL registers? Those are expected. What I meant was that once CRH and CRL in the GPIO are updated, are there any delays before the voltage is output onto the pin? If not, then for a 10 mHz output, I should expect the voltage to be stabilized within 100 nSecs after CRH and CRL are updated?

John F. · ‎2013-09-06

Posted on September 06, 2013 at 09:46

The Data Sheet Doc ID 14611 Rev 8 Figure 46. I/O AC characteristics definition shows the signal transition allowed to meet the ''Maximum frequency'' specification. The

precise

logic of the GPIO output cell is not shown.