STM32F0 How to reset SPI interface?

[matthias2]

Posted on August 15, 2013 at 16:36

Hi,

I've a problem with the SP interface. If I reset continously the uC (maybe interrupting the SPI communication would do the same) sometimes the receive buffer gets a 4-bit offset. I do communicate with 8-bit values. These offset breakdown may hole communication, because I will look for a start delimiter but so a never receive one. I will implement now a detection if I'm in this state. Then I would like to reset the SPI interface or clear the receive buffer. So that the offset will go away. Does anyone have already some experience with that? Saddly there are no steps described in the reference manual. Kind regards Matt #stm32 #discovery #stm32-f0-cortex-m0

[Tesla DeLorean]

Posted on August 15, 2013 at 18:15

Well I don't think there is an explicit method of re-synching SPI, especially when you have a continuous stream. Normally you have discrete bursts, and you'd have a window to reset the controller.

You can send a peripheral reset to the SPI unit, another method on the F0 might be to change up/down the bit width setting of the register in such a way as to pull the device back into synchronization with the stream of data. For this to work you'd have to pluck your preamble/sync data from the stream, and figure out how many bits you're off by.

[dthedens23]

Posted on August 15, 2013 at 21:01

The device should have a Chip Select.  The micro selects the device and then starts transfers.

CS normally is active low.  CS should have a pull up resistor so that the device is not selected at power up or reset (because power up reset state of a GPIO is an input)then change CS pin to output and drive it low.

[matthias2]

Posted on August 16, 2013 at 08:39

Hi clive,

I would like to send a peripheral reset to the SPI as you mentioned. Can you explain to me how I have to do this? Kind regards, Matt

[matthias2]

Posted on August 16, 2013 at 08:44

Hi,

I got some new experience. I saw that the SPI-RX-interrupt are ignored sometimes. I guess it depends when the STM32F0 starts up. This is my initialization: ***

  SPI_I2S_DeInit(SPIx);

  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;   SPI_InitStructure.SPI_DataSize = SPI_DATASIZE;   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;   SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;   SPI_InitStructure.SPI_CRCPolynomial = 7;       /* Configure the SPI interrupt priority */   NVIC_InitStructure.NVIC_IRQChannel = SPIx_IRQn;   NVIC_InitStructure.NVIC_IRQChannelPriority = 1;   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;   NVIC_Init(&NVIC_InitStructure);       /* Initializes the SPI communication */   SPI_I2S_DeInit(SPIx);   SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;   SPI_Init(SPIx, &SPI_InitStructure);          // try to clear flags     SPI_ReceiveData8(SPIx);     SPI_ReceiveData8(SPIx);     SPI_I2S_GetITStatus(SPIx, SPI_I2S_IT_OVR);     SPI_I2S_GetITStatus(SPIx, SPI_I2S_IT_RXNE);     /* Initialize the FIFO threshold (SPI_RxFIFOThreshold_QF = 8-bit)*/   SPI_RxFIFOThresholdConfig(SPIx, SPI_RxFIFOThreshold_QF);   /* Enable the Rx buffer not empty interrupt */   SPI_I2S_ITConfig(SPIx, SPI_I2S_IT_RXNE, ENABLE);     /* Disable the SPI Error interrupt */   SPI_I2S_ITConfig(SPIx, SPI_I2S_IT_ERR, ENABLE);   /* Disable the Tx buffer empty interrupt */   SPI_I2S_ITConfig(SPIx, SPI_I2S_IT_TXE, DISABLE);   /* Enable the SPI peripheral */   SPI_Cmd(SPIx, ENABLE); *** Thanks for help Matt