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STM32F0 Analog/Digital supply power up sequence, rise time rates?

info2399
Associate II
Posted on October 19, 2013 at 05:31

I'm new to the ST product line.  While reading the datasheet for the STM32F051 I came across the following in section 3.5.1 ''Power supply schemes'':

The VDDA voltage must always be greater or equal to the VDD voltage level and must be provided first.

 

 

I haven't been able to determine what ''first'' means.  If VDD and VDDA are connected to the same 3.3V supply, so they both power up and down at the same time, is that good enough?  Do I need to do something to somehow enforce a VDDA-first sequence?  If that's the case, where is the necessary timing defined?

In section 6.3.2 ''Operating conditions at power-up/power-down'', Table 21 shows minimum VDD and VDDA fall times of 20 us/V.  Again, is this something I need to enforce?  Under normal circumstances the capacitors on the power rails would give plenty of fall time.  However, what happens if the 3.3V power supply is accidentally shorted resulting in a very rapid fall time?  Will the chip be damaged?

Thank you very much in advance.

Best regards,

Norman

2 REPLIES 2
Amel NASRI
ST Employee
Posted on October 21, 2013 at 12:53

Hi Norman,

In case you are using a single power supply, VDDA must be externally connected to VDD. it is recommended to use an external filtering circuit in order to ensure a noise free VDDA.

There is another recommendation to keep safe potential difference between VDDA and VDD during power-up/power-down: use an external Sckottky diode between VDD and VDDA.

Regarding the VDD & VDDA fall time rate, if you are respecting the General operating conditions (Table 20), you shouldn't get a value less than 20 µs/V and your chip is safe.

-Mayla-

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info2399
Associate II
Posted on October 22, 2013 at 06:49

Thank you Mayla, that's very helpful.

Best regards,

Norman