SMTM32F4 ETH driver

[francescatodiego]

Posted on November 18, 2013 at 18:22

I am a beginner with STM32F4 and I am study the ETH driver procedure but I don't understand some instructions

For example:   /* Clear MBC bits in the selected MAC address  high register */   (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);     /* Wait until the write operation will be taken into account :    at least four TX_CLK/RX_CLK clock cycles */   tmpreg = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr));   _eth_delay_(ETH_REG_WRITE_DELAY);   (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; I don't understand the read and write same register after delay  Thanks in advance for help #stm32f4-eth

[Tesla DeLorean]

Posted on November 18, 2013 at 18:37

You'd need to find someone with a gate-level understanding of the design to talk to you, but the comments seem to suggest that there are consideration which fall under a different, slower, timing domain than the APB/AHB you are using to access the registers. ie pulling the bits off the wire, and checking the MAC address

[eugene1]

Posted on February 04, 2014 at 23:46

It's a silicone bug workaround. See latest errata sheet ''2.7.5 Successive write operations to the same register might not be fully taken into account''.

[francescatodiego]

Posted on February 05, 2014 at 15:39

Thanks, thanks a lot trushkin now is clear