stm32f07 jlink problem

[razmjoo_89]

Posted on December 01, 2013 at 13:06

hello all

i try to connect stm32f07vct  to jlink but get this error TDO IS CONSTANT HIGH hear is my schematic: http://www.4shared.com/rar/Uavof1vt/f107.html in your opinion what is my problem ? regards

[Tesla DeLorean]

Posted on December 01, 2013 at 17:38

The pin numbering of your JTAG header is all messed up, hopefully the physical manifestation gets the signals where they are supposed to be. In terms of orientation the signals look to be in the right places, so there is hope.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0499b/BEHEIHCE.html

The J-Link pushes 5V out the DBGACK pin, I wouldn't loop that back to DBGRQ I'd probably have a pull up on NRST, and have VREF pins connected to supplies. Check the state on NRST Beyond the JTAG/SWD mechanism the primary signs-of-life test is to strap BOOT0 high and connect USART1 on PA9/PA10, sending 0x7F at 9600 8E1, and looking for a 0x79 response. By default the processor is not going to enable the external oscillators.