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PLL Clock Problem

thirukannan
Associate II
Posted on June 26, 2014 at 12:24

Hi,

I am using stm32l152r8 in my custom board.In this while I running the code I am getting error which is can not access the memory. After some time i found the error which is

if ((RCC->CR & RCC_CR_HSERDY) != RESET)

there in

static void SetSysClock(void) function. if I make it

if ((RCC->CR & RCC_CR_HSERDY) == RESET)

working fine.But I don't know what is the exact problem in this clock setting. Please clear it what is the problem.

Below is the code and i highlighted the error line.

static void SetSysClock(void)

{

  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

 

  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/

  /* Enable HSE */

  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

 

  /* Wait till HSE is ready and if Time out is reached exit */

  do

  {

    HSEStatus = RCC->CR & RCC_CR_HSERDY;

    StartUpCounter++;

  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if ((RCC->CR & RCC_CR_HSERDY) !=RESET)

  {

    HSEStatus = (uint32_t)0x01;

  }

  else

  {

    HSEStatus = (uint32_t)0x00;

  }

 

  if (HSEStatus == (uint32_t)0x01)

  {

    /* Enable 64-bit access */

    FLASH->ACR |= FLASH_ACR_ACC64;

    

    /* Enable Prefetch Buffer */

    FLASH->ACR |= FLASH_ACR_PRFTEN;

    /* Flash 1 wait state */

    FLASH->ACR |= FLASH_ACR_LATENCY;

    

    /* Power enable */

    RCC->APB1ENR |= RCC_APB1ENR_PWREN;

 

    /* Select the Voltage Range 1 (1.8 V) */

    PWR->CR = PWR_CR_VOS_0;

 

    /* Wait Until the Voltage Regulator is ready */

    while((PWR->CSR & PWR_CSR_VOSF) != RESET)

    {

    }

        

    /* HCLK = SYSCLK /1*/

    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

 

    /* PCLK2 = HCLK /1*/

    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

    

    /* PCLK1 = HCLK /1*/

    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;

    

    /*  PLL configuration */

    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |

                                        RCC_CFGR_PLLDIV));

    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);

    /* Enable PLL */

    RCC->CR |= RCC_CR_PLLON;

    /* Wait till PLL is ready */

    while((RCC->CR & RCC_CR_PLLRDY) == 0)

    {

    }

        

    /* Select PLL as system clock source */

    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

    /* Wait till PLL is used as system clock source */

    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)

    {

    }

  }

  else

  {

    /* If HSE fails to start-up, the application will have wrong clock

       configuration. User can add here some code to deal with this error */

  }

}

Thanks & Regards,

Thirukkannan.P
1 REPLY 1
Posted on June 26, 2014 at 13:38

Are you sure your HSE crystal is starting? If it doesn't start properly, because of circuit characteristics, or whatever, it will fall out of the time out loop. It could just not start, or be slow to start.

Putting a probe on the circuit will change it's characteristics, it is possible to route the HSE clock via an MCO pin (PA8), and you could put that on a scope.
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