I2S clock frequency problem

[usama]

Posted on February 07, 2014 at 08:24

Hi,

I am interfacing TLV320AIC3204 to stm32f415, at this stage i am able to configure codec IC using I2C successfully and also able to operate I2S interface in full duplex mode with DMA on both transmission and reception, problem i am having is with generating correct sampling frequency. I am trying to set Fs = 48KHz. Controller is operating on HSE=8MHz with controller PLL enabled and also I2SPLL with PLL_M = 8 ; PLL_N = 336 ; PLL_P = 2 ; PLL_Q = 7 ; PLLI2S_N = 258; PLLI2S_R = 3;i have verified controller is indeed operating at 168MHz and also all the PLL dividers and multipliers are set of the correct value which i set using the system file. which makes I2SCLK = 86MHz. Everything is fine till this point but according to specifications which i mentioned in system_stm32f4xx.c I2SDIV = 3 and ODD =1; but when i check in the debugger for these bits i see I2SDIV to be set to '11' and ODD = 0; using these values if i calculate Fs theoretically i get 15.269KHz and that is the same frequency which i get practically (i verified using MCLK pin which is 256*Fs). Can anyone kindly mention any CMSIS API to manually set ODD=1 and I2SDIV =3, (or any other method), any help would be highly appreciated. Waiting for ur kind response. #full-duplex #i2s #stm32 #dma

[waclawek.jan]

Posted on February 07, 2014 at 11:18

I2SDIV and ODD are fields in the SPI_I2SPR register. If you have set them in

system_stm32f4xx.c and they have changed, you might have overwritten them by calling 

I2S_Init() later. JW

[usama]

Posted on February 07, 2014 at 12:10

yes indeed that was the case, i hard coded correct values in I2S_Init() and now it is working fine. Thanks

[em3ly]

Posted on November 04, 2015 at 16:39

Hello, I have a similar problem (i2s clock configuration) but with stm32f4 Discovery. I hope you can help me, this is driving me crazy. 

I recently bought a STM32F4 discovery and I'm interested in audio processing. I started trying to record some audio data using the MP45DT02 and the I2S module.

The program is based on the play and record demo, it records the audio data and send it to the pc through usb.

With 16kHz of sample frequency it works but with,for example, 48kHz the generate .wav seems to have noise almost like if there were something wrong with the rcc configuration or i2s sample frequency configuration, kike when the audio is playing to a different frequency that the one that was recorded. Ofcourse I modified the size of pdm and pcm buffers according to datasheet, also I generated a new system_stm32f4xx.c with the excel tool (new PLL configuration). Also i manually set i2sdiv and odd,But still does not work.if you could help me, I'd appreciate.

My main.h now looks like this:

#define DECIMATION_FACTOR 

64

#define SAMPLE_FREQUENCY 

48000

#define OUT_FREQ 

SAMPLE_FREQUENCY/2

#define INPUT_CHANNELS

 1

#define PDM_Input_Buffer_SIZE

 (OUT_FREQ / 1000 *DECIMATION_FACTOR

* INPUT_CHANNELS/8 )

#define PCM_Output_Buffer_SIZE

 (OUT_FREQ / 1000 * INPUT_CHANNELS)

#define Buffer_Input_SIZE 

 2048

#define VOLUME 

50

The PDM filter initialization :

Filter.Fs = SAMPLE_FREQUENCY;

Filter.HP_HZ = 10.;

Filter.LP_HZ = (SAMPLE_FREQUENCY / 2.0);

Filter.In_MicChannels = 1;

Filter.Out_MicChannels = 1;

PDM_Filter_Init(&Filter);

The i2s configuration:

SPI_I2S_DeInit(SPI2);

I2S_InitStructure.I2S_AudioFreq = SAMPLE_FREQUENCY * 2;

I2S_InitStructure.I2S_Standard = I2S_Standard_LSB;

I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;

I2S_InitStructure.I2S_CPOL = I2S_CPOL_High;

I2S_InitStructure.I2S_Mode = I2S_Mode_MasterRx;

I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;

I2S_Init(SPI2, &I2S_InitStructure);

// Enable the Rx buffer not empty interrupt

SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, ENABLE);

And all these are the configurations generated in system_stm32f4xx.c

*-----------------------------------------------------------------------------

System Clock source | PLL (HSE) *-----------------------------------------------------------------------------

SYSCLK(Hz) | 168000000 *-----------------------------------------------------------------------------

HCLK(Hz) | 168000000 *-----------------------------------------------------------------------------

AHB Prescaler | 1 *-----------------------------------------------------------------------------

APB1 Prescaler | 4 *-----------------------------------------------------------------------------

APB2 Prescaler | 2 *-----------------------------------------------------------------------------

HSE Frequency(Hz) | 8000000 *-----------------------------------------------------------------------------

PLL_M | 8 *-----------------------------------------------------------------------------

PLL_N | 336 *-----------------------------------------------------------------------------

PLL_P | 2 *-----------------------------------------------------------------------------

PLL_Q | 7 *-----------------------------------------------------------------------------

PLLI2S_N | 384 *-----------------------------------------------------------------------------

PLLI2S_R | 2 *-----------------------------------------------------------------------------

I2S input clock(Hz) | 192000000

|

To achieve the following I2S config: |

- Master clock output (MCKO): OFF |

- Frame wide : 16bit |

- Audio sampling freq (KHz) : 48 |

- Error % : 0.0000 |

- Prescaler Odd factor (ODD): 1 |

- Linear prescaler (DIV) : 62 | *-----------------------------------------------------------------------------

VDD(V) | 3.3 *-----------------------------------------------------------------------------

Main regulator output voltage | Scale1 mode *-----------------------------------------------------------------------------

Flash Latency(WS) | 5 *-----------------------------------------------------------------------------

Prefetch Buffer | OFF *-----------------------------------------------------------------------------

Instruction cache | ON *-----------------------------------------------------------------------------

Data cache | ON *-----------------------------------------------------------------------------

Require 48MHz for USB OTG FS, | Enabled

SDIO and RNG clock | *-----------------------------------------------------------------------------