Posted on May 31, 2015 at 17:49I don't quite understand what's your problem, but maybe this will help: in the 16- and 32-bit SRAMs always a whole word (halfword, whatever) is addressed and transferred. The address thus lacks the less significant bits of a bytewise address. So, if you want to read say from a 32-bit SRAM a byte from bytewise address 0x4321, you put 0x10C8 onto the address bus, read in the whole word and then pick byte 1 from it. The FSMC/FMC allows you to read a 32-bit value from unaligned addresses; so if you want to read a word from the same address, the controller puts 0x10C8 to the address bus, reads the word, picks the 3 upper bytes from it, then it puts 0x10C9 to the address bus, reads the word, and picks the lowermost byte from it, stitches it all together and hands it over to the processor - this is all seamless for the software, except that it takes longer than accessing a word on aligned address.
Writing is similar, except that the processor has to ''tell'' to the memory somehow, which bytes to take into account - and this is the role of the ByteLane (NBLx) signals. So, in case of aligned writes, all NBLx signals go low in the single cycle the write takes; in case of unaligned writes, there are two cycles, with the uppermost NBLx signals going down in first, the lowermost in the second (with the higher word address).
JW
