Posted on February 12, 2014 at 00:04
Yes, thank you. That's a mistake and I've updated my source:
/* Enable peripheral clocks for SPI and DMA */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
That takes care of the issue I described in the original post. Thanks!
A couple more points:
1) The frame received contains 1119 bytes of 0xFF. I'll look into the FPGA serial configuration. If you see anything in my SPI configuration that may relate to this please let me know.
2) An issue I'll note that's not as related: even with the correct clock enabled, the DMA interrupt was not being generated consistently... The transmission was being triggered by a reset button on the FPGA board without debounce circuitry. I assume since the clock signal was jittery from the push button, DMA/SPI was not detecting a half or full frame transmission.Power cycling the FPGA without the button results in a clean signal and DMA interrupts are generated every time.
