DMA FIFO Flush Issue

szarovy · ‎2014-02-20

Posted on February 20, 2014 at 18:00

I am using a STM32F4 as a SPI slave. The STM32F4 receives a packet of data over a USART line and must have the data immediately available for use in the SPI communication. I am using a DMA Tx memory to peripheral transfer on the SPI line to quickly shift out data. In order to make the fresh data immediately available to the SPI DMA I am attempting to flush the DMA FIFO buffer to remove the data that was automatically loaded into the buffer after the previous SPI transfer. I reset the EN bit of the DMA register to start the FIFO flush and a little bit later the DMA TCIF bit is set which I think is suppose to signify the flush is complete. However after enabling the DMA again, in the next SPI transfer, the data is incorrect. The first byte sent is the last byte from the previous SPI transfer, the second byte is the first byte of the new data packet, and the third byte is the second byte of the new data packet and so on. I am thinking I am simply not flushing the FIFO buffer and re-enabling the DMA stream properly. I have checked the remaining data counter, DMA_SxNDTR and it shows full number of bytes after a flush. I am not sending too big of a data packet (only 96 bits) but I am stuck in the structure of needing to act as a SPI slave and receive fresh data in real time. Any tips or suggestions would be greatly appreciated.

#stm32f4 #dma_fifo

waclawek.jan · ‎2014-02-20

Posted on February 20, 2014 at 18:39

Sounds suspiciously similar to https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fChecking%20for%20finished%20SPI%20%20DMA%20transfer%20-%20missing%20data&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F...

What about creating a simple test case, demonstrating the problem; ideally on something like the DISCOVERY or EVAL board, mimicking the UART-triggered-event by a pushbutton, and using an other SPI on the same chip as the master?

JW

szarovy · ‎2014-02-21

Posted on February 21, 2014 at 19:07

I have been using a Discovery board to develop my code and I've been testing with the another STM32 Discovery board acting as the SPI Master. I can try to have it write to another SPI on the same chip but that would seem to be very similar to what I'm doing now. If there any other checks I can do besides seeing the TCIF is set after I start a FIFO flush?

grant · ‎2015-06-16

Posted on June 16, 2015 at 11:39

(I have also replied in the other thread but put this here for anyone looking in the future)

Hi there

I have been running an STM32F207 with:

SPI running in slave mode
using DMA

and also had the problem where the first word (I am using

16 bit transfers

) was corrupted, or simply not there.

I believe I may have found the solution. The problem is that nothing seems to trigger the FIRST load from the DMA into the SPI DR, and it is not until after the first 16 bits have been clocked out that the DMA controller does the first transfer into the DR of the SPI Channel. So it behaves more like as in ''Figure 262: Reception using DMA'' in the STM32F207 Reference Manual.

I got around this by :

manually loading the first word from into the DR of the SPI channel
configuring the DMA channel to start at the next word in my buffer (obviously reducing the length by 1 word)

It seems to work fine in my application. Hope this helps.

Regards

Grant