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Backup SRAM content lost in VBAT-mode

mats
Associate
Posted on February 28, 2017 at 12:09

Are VCAP_1 and 

VCAP_2 used in Vbat-mode?

I have an issue with the content of the Backup SRAM is lost when i power down the device, even though the Vbat is active.

If i do a reset the content of backup SRAM and RTC-registers remain. But if i remove Vdd for a few ms the content of the backup SRAM becomes garbage but the 

RTC

-registers are not affected.

I have checked with an oscilloscope that the voltage at Vbat never drops below 3.1 Volts.

I have enabled the backup regulator with a call to 'HAL_PWREx_EnableBkUpReg()'. I have also checked that the BRE and BRR flags gets set in the PWR->CSR register.

My theory that i hope someone can confirm or discard:

Backup SRAM does not work in 'BYPASS_REG'-mode.

I use my own 1.2Volt regulators connected to VCAP_1 and

VCAP_2 

and have pin 'BYPASS_REG' hardwired to 3.3 Volts in normal mode.

When i power down Vdd, 

VCAP_1, 

VCAP_2

 and BYPASS_REG are pulled low.

After a power cycle the 'Backup regulator enable' in register 'PWR power control/status register' is still set, but the 'Backup regulator ready' takes some time before it becomes set. I believe this indicates that there is some issue with the power...

I use a STM32F429

#stm32f429 #sram-backup-rtc #bypass_reg
3 REPLIES 3
Posted on February 28, 2017 at 12:30

How's your VCAP1, 2 -- PA0 -- NRST sequencing, up and down?

JW

mats
Associate
Posted on March 01, 2017 at 09:05

Here are the startup and shutdown sequence.

Ch1-Yellow: 1.2V connected to Vcap_1 and 

Vcap_2

Ch2-Cyan: NRST (PA0)

Ch3-Purple: 3.3V connected to Vdd.

Ch4-Blue: VBAT

0690X00000606RbQAI.png

Startup (100ms recording)

0690X00000606S5QAI.png

Shutdown (10ms

recording

)
Posted on March 01, 2017 at 11:23

Then this is the problem.

You MUST hold both reset and PA0 low long enough until V12 and VDD gets stable, and you must pull them low soon enough when they start to fall.

See the Startup in regulator OFF mode: fast V DD slope- power-down reset risen before V CAP_1 /V CAP_2  stabilization figure in DS.

JW