Posted on March 25, 2014 at 22:50The data sheet makes no explicit mention of a way to force this interrupt to latch and clear when the CLICK_SRC register is read (like the INT1_CFG registers can).
App note AN3308 states that this behavior can be achieved by setting the LIR bit in the TAP_CFG register. However, this bit is not documented in the data sheet. Another, similar part perhaps?
I'm seeing the interrupt hold for the duration of the CLICK_LATENCY period as expected but would like to clear this sooner as I'm using the data ready signal on the same line. Is there anything I can do to accomplish this? I'm sampling at a fairly low data rate (10hz) so shortening the latency period is not an option. I am using an OEM board that does not have INT2 hooked up.
#li3dh-click
