STM32F4 DMA Interrupt big latency :(

[eittinfo]

Posted on April 04, 2016 at 01:43

Hi everybody

i work on a project and in my project dma sync by timer1 and timer1 as config for pwm and dma trigger on update event.

i have a big problem.

my total transient is cost and after finish dma must stop timer to disable output pwm .

but when dma intruppt triggered ,after 3-4 extra clock timer1 disabled and it make problem for me becuase i loss sync data transfered with pwm pulse

do you have any idea about this issus

my pwm freq around 16Mhz and if i redused it under 8Mhz this problem not happened again

i have problem about it

tnx for attention

[Tesla DeLorean]

Posted on April 04, 2016 at 03:05

Perhaps you can better explain the clock/data waveform and length you are trying to generate, and the code you have now.

What I'm hearing now is that the last DMA writes to memory, then generates a TC interrupt, and then you finally disable the timer. Yes, of course there is going to be some latency there, a few dozen clock cycles (168/24 = 7 MHz). You'd probably want to look at how you can get the hardware to limit the count, perhaps a timer in One Pulse mode, and a Repetition Count?

[eittinfo]

Posted on April 04, 2016 at 11:55

Tnx for replay.

yes you hear right 🙂i want transfer some data from sram to peripheral and use timer1 to tigger dma request and sync dma transfer rate and config timer1 ocr to build pwm signal use for a output clk signal.when dma generate transfer complete (TC) ,i must stop timer1 working to disable output clk signal,but when interrupt function happen,after some cycle timer disabled,i use direct register access to disable timer,but it's seems interrupt latency make this problem,and i have some extra clock in output as pwm pin,this problem happen when i increase clock freq higher than ~8Mhz.i put interrupt routin on sram but problem not solved and some new extra clk happen.i hope could explain my means 🙂i have problem with huge interrupt latency,tnx for replay clive1 🙂