Any easy way to tell if LSE lock is lost while running: STM32F205

[Taylor.Sean]

Posted on March 21, 2016 at 17:25

We have a batch of boards in the field where the LSE crystal may be marginal and I'm wondering if there's a way to check for the LSE losing lock after initially being locked.  That is, if on initial clock setup I get a positive response from RCC_GetFlagStatus(RCC_FLAG_LSERDY), but later the LSE stops.

I've looked at the RCC_BDCR register and it doesn't seem to change, even if I short out the crystal, but I do see the RTC stop advancing.So is my only option to check for the RTC stopping advancing and use that to flag a problem ?   Thanks in advance

[waclawek.jan]

Posted on March 21, 2016 at 17:45

> I've looked at the RCC_BDCR register and it doesn't seem to change, even if I short out the crystal, but I do see the RTC stop advancing.

Yes, unfortunately LSE_RDY flag does not seem to reflect the true state of LSE, serving only as a startup indicator. I guess it's just an output from a saturated fixed-count counter fed by LSE. Some newer STM32 models (e.g. 'L0, I did not check elsewhere) feature a LSE-CSS, but not the 'F2/'F4. You might perhaps want to check out the 'L4. RTC output event may be fed into TIM5_CH4, see TIM5_OR, but I don't know exactly could that be used for any automatism to check LSE running. JW

[jpeacock]

Posted on March 21, 2016 at 17:55

If you use the SysTick timer as a timebase, for example in an RTOS, and you generate a 1 second t interrupt from the RTC, then if you get 2 seconds worth of SysTicks but no RTC  you can conclude the LSE failed.

I also reset the IWDG from the 1 second RTC since an LSE failure is a fatal event in my applications.  After a reset if you see the IWDG as the source you know the RTC isn't working and can fall back to the LSI as a workaround.

[Taylor.Sean]

Posted on March 21, 2016 at 19:26

Thanks guys.   I'll use the SysTick interrupt to monitor the RTC and restart it on the LSI if I notice a loss of ticking.   That will suffice for almost all functionality.

[Tesla DeLorean]

Posted on March 21, 2016 at 20:30

RTC output event may be fed into TIM5_CH4, see TIM5_OR, but I don't know exactly could that be used for any automatism to check LSE running.

You can use it to measure the period, or up to 8 periods, of the LSI, or LSE. In a 1ms ticker, you'd expect this timestamp (in TIM5->CCR4) to precess.

[waclawek.jan]

Posted on March 21, 2016 at 22:11

By ''automatism'' I meant ''no stinkin' software-checking-periodically, just interrupt me when the clock stops''. Should that channel be CH1 or CH2, I'd tie it to the slave controller and reset the timer from RTC; then set another channel to interrupt just beyond the one second mark. Maybe something similar could be accomplished by employing a DMA triggered by CH4, writing a well-chosen constant to some of the timer's registers.

JW