STM32F429 NAND conflict withSDRAM

zeus_zhn · ‎2014-10-21

Posted on October 21, 2014 at 09:55

I have a board based on the stm32f429. There is a 16M Bytes SDRAM (MT48LC16M8) and a 32M bytes NAND (NAND128W3A2B) connected to the FMC bus.

I used one area of the SDRAM as the LTCD buffer,such as:

/* Start Address configuration : the LCD Frame buffer is defined on SDRAM */

LTDC_Layer_InitStruct.LTDC_CFBStartAdress = LCD_FRAME_BUFFER;

There is two strange problem:

[1] The nand write/read is always unstable, sometimes went wrong. After months of trying, I finally found that:

The nand operation is ok if I turn off the LTDC controller, namely not using the SDRAM as frame buffer. the command is:

LTDC_Cmd(ENABLE);

[2] Even I turn off the LTDC controller, if I use the upper 8M bytes of sdram, the nand still generates write error.

To summarize:

The only working nand operation is to satisfy both:

a. Turn off the LCD controller;

b. configure the SDRAM as using 8M bytes only:

FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_9b;

FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;

If I configure to use the whole 16M SDRAM like:

FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_10b;

FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;

nand will go wrong.

I have researching this problem for months, can't find the answer, could anyone help me out. Even a hint maybe will help me find the solution.

Thank you very much!

If I only use the

Tesla DeLorean · ‎2014-10-21

Posted on October 21, 2014 at 10:07

What Address bits does the NAND use to differentiate between the command/data interfaces? What timing/stability requirements does the NAND have wrt the data and address buses?

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zeus_zhn · ‎2014-10-21

Posted on October 21, 2014 at 10:13

Both nand and sdram are 8 bits.

For Nand, i mm using the wait feature, the configuration is:

p.FMC_SetupTime = 0x1;

p.FMC_WaitSetupTime = 0x3;

p.FMC_HoldSetupTime = 0x2;

p.FMC_HiZSetupTime = 0x1;

FMC_NANDInitStructure.FMC_Bank = FMC_Bank2_NAND;

FMC_NANDInitStructure.FMC_Waitfeature = FMC_Waitfeature_Enable;

FMC_NANDInitStructure.FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_8b;

FMC_NANDInitStructure.FMC_ECC = FMC_ECC_Disable;

FMC_NANDInitStructure.FMC_ECCPageSize = FMC_ECCPageSize_512Bytes;

FMC_NANDInitStructure.FMC_TCLRSetupTime = 0x00;

FMC_NANDInitStructure.FMC_TARSetupTime = 0x00;

stm322399 · ‎2014-10-21

Posted on October 21, 2014 at 10:23

Could this problem be related to that one ? FMC on F429 has an errata.

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy.st.com%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fSTM32F429%20FMC%20SDRAM%20problem&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&cur...

waclawek.jan · ‎2014-10-21

Posted on October 21, 2014 at 11:07

> Could this problem be related to that one ? FMC on F429 has an errata.

+1

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy.st.com%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fSTM32F429%20Silicon%20Revision%203%20ETA&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506...

JW

zeus_zhn · ‎2014-10-21

Posted on October 21, 2014 at 14:38

I am not sure if I understanding this errota correctly, does this mean:

SDRAM and NAND cannot be used at the same time in some chip production version?

zeus_zhn · ‎2014-10-22

Posted on October 22, 2014 at 09:46

Could anyone explain what does this workaround means regarding to the ''FMC dynamic and static bank switching''

Description

The dynamic and static banks cannot be accessed concurently.

Workaround

Do not use dynamic and static banks at the same time. The SDRAM device must be in self-refresh before switching to the static memory mapped on the Nor or NAND controller.

Before switching from static memory to SDRAM, issue a normal command to wake-up the device from self-refres mode.

Does my situation means ''concurrently access'':

reading/wring from NAND while the LTDC using SDRAM as framebuffer. The nand is using BANK 2, the SDRAM is using bank 5.

waclawek.jan · ‎2014-10-22

Posted on October 22, 2014 at 10:38

Unfortunately, yes. The errata means, that to use NAND, you need to stop using SDRAM, and vice versa.

JW

zeus_zhn · ‎2014-10-22

Posted on October 22, 2014 at 11:23

That doesn't make sense, because I can read/write nand directly to a SDRAM area if turn off the LTDC controller. Like:

u8 pcDest[0x100000] __attribute__((at(0xc0200000)));

uffs_read(fd, pcDest, header.ulFileSize);

zeus_zhn · ‎2014-11-18

Posted on November 18, 2014 at 15:06

So the only solution for me is to wait the version 3 chip?