WWDG Interrupt

[budde2]

Posted on September 04, 2009 at 23:34

WWDG Interrupt

[budde2]

Posted on May 17, 2011 at 13:22

Hi,

I am just trying to set up the watchdog for my system. My watchdog code is more or less a copy of the WWDG example in the firmware library. The WWDG interrupt is used to reset the watchdog counter. As long as my system is idle everything works like expected. If there is a lot of load on the system (e.g. DMA transfers and other interrupts) my system executes a reset very often. I have set the WWDG interrupt to priority 0 and all other interrupts (I2C, DMA, UART, TIM, SysTick) to priority 1. I think the problem is caused by the fact that the WWDG interrupt handler is executed to late. Does anybody know how to solve this problem? I think the design of the STM32's watchdog is a little bit strange. The WWDG interrupt it generated when the counter equals 0x40. One tick later at 0x3f the STM32 executes a reset. Maybe it would make more sense that the interrupt comes earlier (e.g. at 0x50)?

[16-32micros]

Posted on May 17, 2011 at 13:22

Hi,

This is an expected behavior 🙂 Note that in STM32F1xx , you have two different watchdogs : 1) ''Independent'' watchdog (IWDG) - Is clocked from an independent RC oscillator (can operate in Standby and Stop modes) - Resets (if watchdog activated) when the downcounter value of 0x000 is reached 2) ''Window'' watchdog (WWDG) : - Resets (if watchdog activated) when the downcounter value becomes less than 40h – Resets (if watchdog activated) if the downcounter is reloaded outside the window For more details on how they are working , Please go to RM0008 ( rev9) Section 17 and 18. In you case I think that you should use IWDG instead of WWDG. Cheers, STOne-32.