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Doubt about window watchdog timer

DUrbano
Associate III
Posted on October 28, 2014 at 12:06

Hi,

I'm working on stm32f4cc and I'm trying to learn the functionalities of window watchdog timer, but after read all about this on reference manual and tried a simple code some doubts rise. I configured the mcu in this mode: - APB1 clock: 16MHz; - WDG prescaler: 8; - Window value: 0x7e; - Counter value: 0x7f. and I use the EWI interrupt. Reading from reference manual, I know the counter starts to 0x7f and descrementing every (1/16e6)*4096*8 clock counts, it falls down to 0x3f when (bit 6 = 0) the interrupt raises. So I expect a timing of about: (1/16e6)*4096*8*(0x7f-0x3f) = 131ms. This is my simple code:

/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_USART1_UART_Init();
MX_WWDG_Init();
/* USER CODE BEGIN 2 */
HAL_UART_Transmit(&huart1, (uint8_t *)&
''$''
, 1, 15);
HAL_Delay(1000);
HAL_UART_Transmit(&huart1, (uint8_t *)&
''All is ready''
, 12, 15);
/* USER CODE END 2 */
/* USER CODE BEGIN 3 */
/* Infinite loop */
while
(1)
{
HAL_Delay(500);
HAL_UART_Transmit(&huart1, (uint8_t *)&
''.''
, 1, 15);
if
(f_wwdgEnable)
{
HAL_UART_Transmit(&huart1, (uint8_t *)&
''\r\nStart watchdog timer''
, 22, 15);
HAL_Delay(100);
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_5); 
HAL_WWDG_Start_IT(&hwwdg); 
f_wwdgEnable = 
false
; 
}
}

where by an external interrupt to the PB0 pin, I set the boolean f_wwdgEnable, so in the while(1) code, it's possible to start the watchdog timer; when it starts, the PB5 pin goes high till the WWDG interrupt raises when the PB5 pin goes low. Using an oscilloscope, I note the timing of multiple and consecutive test is not equal but varies from time to time and it's not ever equal to the former. These are the funtions to init and start the WWDG:

HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
{
/* Check the WWDG handle allocation */
if
(hwwdg == NULL)
{
return
HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); 
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); 
if
(hwwdg->State == HAL_WWDG_STATE_RESET)
{
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
}
/* Change WWDG peripheral state */
hwwdg->State = HAL_WWDG_STATE_BUSY;
/* Set WWDG Prescaler and Window */
MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
/* Set WWDG Counter */
MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
/* Change WWDG peripheral state */
hwwdg->State = HAL_WWDG_STATE_READY;
/* Return function status */
return
HAL_OK;
}
HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
{
/* Process Locked */
__HAL_LOCK(hwwdg); 
/* Change WWDG peripheral state */
hwwdg->State = HAL_WWDG_STATE_BUSY;
/* Enable the Early Wakeup Interrupt */
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
//DUR
__HAL_WWDG_ENABLE_IT(WWDG_IT_EWI);
/* Enable the peripheral */
//__HAL_WWDG_ENABLE(hwwdg); 
hwwdg->Instance->CR |= (WWDG_CR_T6|WWDG_CR_WDGA);
// DUR
/* | 
|_____bit 6 deve essere posto ad 1 ogni volta 
che si scrive sul registro WWDG_CR
*/
/* Return function status */
return
HAL_OK;
}

I have modified HAL_WWDG_Start_IT because, as I read in the reference manual, every write operation on WWDG_CR register must be accomplished with a bit 6 = 0. please could anyone tell me what's going on ? Regards
1 REPLY 1
howard n2wx
Senior
Posted on May 03, 2017 at 22:52

I have modified HAL_WWDG_Start_IT because, as I read in the reference manual, every write operation on WWDG_CR register must be accomplished with a bit 6 = 0.

FWIW on the 32f302 writing a 0 in bit 6 causes a software reset (reference man section 25.3.2)...