Will DMA restart in circular mode clear previous unfinished array?

cyqdtc · ‎2014-08-04

Posted on August 04, 2014 at 12:22

Dear all,

We are using DMA connecting with an ADC though SPI in circular mode. ADC results will be loaded into array1[320] and arrary2[320].

My question is sometimes I need to stop DMA transmission and restart it later. However, the stop action may happen in the middle of a transmission without filling a destination array. Say arrary1[] is half filled to array1[159]. When the DMA is restarted, will arrary1[] be filled after the previous write, which is array1[159]? Or will arrary1[] be filled from the very beginning at arrary1[0]?

I wish it to be the second condition, since we need some sort of synchronization. If array1[] will not be filled at the very beginning after restart, what should I do to make it like that?

My current way of restart is simply close by clear enable DMA bit; and open by set the enable DMA bit.

Thank you very much.. 🙂

#circular-mode #fifo #dma

schauer · ‎2014-08-04

Posted on August 04, 2014 at 13:58

Hi Richie,

as far as I have read:

If you stop the DMA it is stopped and the next start let it start from the very beginning. In circular mode that means it starts from the beginning.

The only possible solution in my mind is to reconfigure the DMA for a single transfer (until the array is finally handled) and afterwards setup again a circular DMA. Probably it is possible to configure a second stream to handle that situation, so that you just need to enable the circular DMA Stream after the other is finished.

bs

cyqdtc · ‎2014-08-04

Posted on August 05, 2014 at 05:29

Hi bs thanks for your reply.

I just re-read the datasheet : http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00046011.pdf

It says on page 15:

1. If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register,

then read this bit in order to confirm that there is no ongoing stream operation. Writing

this bit to 0 is not immediately effective since it is actually written to 0 once all the

current transfers have finished. When the EN bit is read as 0, this means that the

stream is ready to be configured. It is therefore necessary to wait for the EN bit to be

cleared before starting any stream configuration.

It seems that if I want to restart the DMA and start from the very beginning, I can simply clear the enable bit and wait it to be effective and then open it.

Thanks!

Richie

schauer · ‎2014-08-05

Posted on August 05, 2014 at 10:21

Yes thats correct. Please also keep in mind ''10.3.14 DMA Transfer Suspension'' (STM32F4) from the user manual.

cyqdtc · ‎2014-08-06

Posted on August 07, 2014 at 05:50

Thank you bs! Not only how to start from very beginning I know, now also how to start at the previous position!!