Posted on August 25, 2014 at 16:26Hi
Based on your answer, I don't understand why you asked me if the pins were connected to anything else external... since you say I can't pull them up to VCC anyway...
However, let me explore further...
In figure 1, there is a Logic block in the diagram, but no mention of Vdd or 5V.
In fact, if I painstakingly search the document there is no mention of Vdd anywhere, or that the chip uses 5V logic. (Yes, it's implied by the circuit examples and test conditions, but not stated anywhere). Search for yourself.
Also, on the block diagram, there is a signal clamp function, which seems to be applicable here. In table 9, the ENa and ENb lines show an input clamp between 5.5 and 7.5 V at 1 mA. I assume this is to protect and condition the inputs.
So if I use a 100K pullup to 12V on these inputs, then I'm limiting the input current to 0.06mA so wouldn't the input clamps do their job and reduce the input level to an appropriate voltage? If not, why are the input clamps there?
If I've misinterpreted the sheet, then perhaps some clarification would help out.
Specify the desired/max limits on these pins (Current and voltage)
Phil.
