Posted on November 25, 2014 at 18:58> STM32F407 datasheet says max fsmc clk = 60Mhz
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> FSMC_CLKDivision = 2; // 168/2 = 84Mhz
> FSMC_CLKDivision = 3; // 168/3 = 56Mhz
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> So what is CLKDivision for 60MHz? ??
HCLK is not necessarily 168MHz. If, for example, you set HCLK=120MHz, then you can use FSMC_BTRx.CLKDIV = 2 or above. For HCLK above that, the divider has to be at least 3 and FSMC_CLK will be less than 60MHz. In every case, your synchronous memory has to support that speed.
JW
