stm32l496g_discovery_sd.c hypothesis denied

[Tesla DeLorean]

Posted on June 08, 2018 at 13:19

Bugs in current, and older code trees

STM32Cube_FW_L4_V1.12.0\Drivers\BSP\STM32L496G-Discovery\stm32l496g_discovery_sd.c

...

/**

  * @brief  Initializes the SD MSP.  * @note   The SDMMC clock configuration done within this function assumes that  *         the PLLSAI1 input clock runs at 8 MHz.  * @param hsd: SD handle  * @param Params: Additional parameters  * @retval None  */__weak void BSP_SD_MspInit(SD_HandleTypeDef *hsd, void *Params){  GPIO_InitTypeDef gpioinitstruct = {0};  RCC_PeriphCLKInitTypeDef  RCC_PeriphClkInit;

  /* Prevent unused argument(s) compilation warning */

  UNUSED(Params);

  HAL_RCCEx_GetPeriphCLKConfig(&RCC_PeriphClkInit);

  /* Configure the SDMMC1 clock source. The clock is derived from the PLLSAI1 */

  /* Hypothesis is that PLLSAI1 VCO input is 8Mhz */  RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1;  RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 24;  RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = 4;  RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;  RCC_PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLLSAI1;  if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK)  {    while (1) {}  }

...

The PLL share a common divided clock source via PLLM, in the critical example code for this platform the source is almost always the MSI in Range 6, ie 4 MHz and not an 8 MHz HSE

Resulting in the microSD card being super slow in the primary demo code, 24 MHz at the peripheral, 12 MHz on the wire, instead of twice that.

STM32Cube_FW_L4_V1.12.0\Projects\32L496GDISCOVERY\Applications\FatFs\FatFs_uSD_Standalone\Src\main.c

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/**

  * @brief  System Clock Configuration  *         The system Clock is configured as follows :  *            System Clock source            = PLL (MSI)  *            SYSCLK(Hz)                     = 80000000  *            HCLK(Hz)                       = 80000000  *            AHB Prescaler                  = 1  *            APB1 Prescaler                 = 1  *            APB2 Prescaler                 = 1  *            MSI Frequency(Hz)              = 4000000  *            PLL_M                          = 1  *            PLL_N                          = 40  *            PLL_R                          = 2  *            PLL_P                          = 7  *            PLL_Q                          = 4  *            Flash Latency(WS)              = 4  * @param  None  * @retval None  */void SystemClock_Config(void){  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};  RCC_OscInitTypeDef RCC_OscInitStruct = {0};

  /* MSI is enabled after System reset, activate PLL with MSI as source */

  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;  RCC_OscInitStruct.MSIState = RCC_MSI_ON;  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;  RCC_OscInitStruct.PLL.PLLM = 1;  RCC_OscInitStruct.PLL.PLLN = 40;  RCC_OscInitStruct.PLL.PLLR = 2;  RCC_OscInitStruct.PLL.PLLP = 7;  RCC_OscInitStruct.PLL.PLLQ = 4;  if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)  {    /* Initialization Error */    while(1);  }

...

[Imen.D]

Posted on June 08, 2018 at 16:44

Hello

Turvey.Clive.002

You are right, weconfirm the point in FatFs applications, it is OK for the Demonstrationapplication code main.c where in SystemClock_Config() it is indicated:

RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_7; /*!< MSI = 8 MHz. Do not modify this value used as SAI Source, MMC */

Our development team is aware about this issu, andstudying this point for fix in the coming release of STM32CubeL4.

Thanks and Best Regards,

Imen

[Tesla DeLorean]

Posted on June 08, 2018 at 17:07

The solution I had was to make the PLLSAI1 settings consistent with all the other L4 examples, as I recall several of the L4 NUCLEO's don't connect HSE to the ST-LINK by default.

/* Hypothesis is that PLLSAI1 VCO input is 4MHz MSI */

  RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1;  RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 48; // [7..87] whilst keeping VCO in 64 to 344 MHz range

  RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = 4;

The more hardened approach would be you compute this stuff on the fly so it was adaptive, or to try and keep the clock setting code in a centralized location

[Tesla DeLorean]

Posted on June 08, 2018 at 17:24

Clocking the SDMMC peripheral at 96 MHz yielded 25 MBps reads on a 16GB SAMSUNG eMMC chip

Currently talking to some individuals out of the European WDC/SanDisk office about eMMC support with

Przenioslo.Lukasz

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