STM32f4 Discovery + SSD1963, FSMC

[voltarenjunkie]

Posted on November 04, 2014 at 12:34The original post was too long to process during our migration. Please click on the attachment to read the original post.

[voltarenjunkie]

Posted on November 04, 2014 at 15:58

Hi all,

problem solved. Had issues with the Button_Init and Uart_Init. Now the only problem left is, the screen is mirrored and the colors dont match yet ...

[frankmeyer9]

Posted on November 04, 2014 at 16:10

Now the only problem left is, the screen is mirrored and the colors dont match yet ...

The only hint I can give is to read the SSD1963 specification carefully (especially the configuration register part), and compare it with your actual screen initialisation. It shouldn't be too difficult to find the init values for screen orientation and colour modes. I have done the same (only for other screen controllers). Sometimes (say, often) subvariants differ here on small details. BTW, there is a ''Format Code Block'' icon available when editing your post (upper left icon), which makes code snippets much more readable ...

[voltarenjunkie]

Posted on November 04, 2014 at 21:29

Hi fm,

thanks for your answer! I will try to figure out the init problem tomorrow. Thanks for the hint with the Format Code Button 😉

[voltarenjunkie]

Posted on November 05, 2014 at 11:41

Hi again,

i got the mirrored screen working in the correct way, but i still have color and performance problems. Also i can't figure out how to display an image correctly. The image is converted with the tool vader.darth used in his old project, but i can only see half of the image on the screen. Here is my SSD1963 LCD_init:

/*******************************************************************************

* Function Name : LCD_Initializtion

* Description : SSD1963 Resets

* Input : None

* Output : None

* Return : None

* Attention : None

*******************************************************************************/


void LCD_Init(void)

{

// Reset

GPIO_ResetBits(GPIOB , GPIO_Pin_0);

Delay_ms(300); //changed 300 to 30 2014

GPIO_SetBits(GPIOB , GPIO_Pin_0);

Delay_ms(300); //changed 300 to 10 2014


LCD_WriteIndex(SSD1963_SOFT_RESET); //Software Reset

LCD_WriteIndex(SSD1963_SOFT_RESET); //Software Reset

LCD_WriteIndex(SSD1963_SOFT_RESET); //Software Reset


Delay_ms(500);


//Set_PLL


LCD_WriteIndex(SSD1963_SET_PLL); //START PLL changed from WriteReg to index

LCD_WriteData(0x01); //added 2014

Delay_ms(1000); //required delay

LCD_WriteData(0x03); //LOCK PLL


Delay_ms(5);

LCD_WriteIndex(SSD1963_SOFT_RESET); //Soft replacement

Delay_ms(20);


// Back Light

GPIO_SetBits(GPIOC , GPIO_Pin_7);


Delay_ms(10);



//Set LCD mode, varies from individual manufacturer

LCD_WriteIndex(SSD1963_SET_GDISP_MODE);

LCD_WriteData(0x20); // set 24-bit for AT070TN92 7'' panel

LCD_WriteData(0x00); // set Hsync+Vsync mode changed 0x00 to 0x20 2014

LCD_WriteData((DISP_HOR_RESOLUTION-1)>>8); // Set LCD panel size(DISP_HOR_RESOLUTION = 800) H Changed 480 to 800 2014

LCD_WriteData(DISP_HOR_RESOLUTION-1); // Set LCD panel size(DISP_HOR_RESOLUTION = 800) L Changed 480 to 800 2014

LCD_WriteData((DISP_VER_RESOLUTION-1)>>8); // Set LCD panel size(DISP_VER_RESOLUTION = 480) H Changed 272 to 480 2014

LCD_WriteData(DISP_VER_RESOLUTION-1); // Set LCD panel size(DISP_VER_RESOLUTION = 480) L Changed 272 to 480 2014

LCD_WriteData(0x00); //0x00 // RGB sequence

Delay_ms(5);


/* added 2014

* For a 10MHz reference clock to obtain 115MHz PLL frequency, user cannot program N = 23 and M = 2. The closet

setting in this situation is setting N=34 and M=3, where 10 x 34 / 3 = 33MHz.


WRITE COMMAND “0xE2�?

WRITE DATA “0x21�? (N=34)

WRITE DATA “0x02�? (M=3)

WRITE DATA “0x54�? (Dummy Byte)

*/

LCD_WriteIndex(SSD1963_SET_PLL_MN); //Set PLL with OSC = 10MHz (hardware), Multiplier N = 35,

//250MHz < 
VCO
< 
800MHz
= 
OSC
*(N+1), 
VCO
= 
360MHz

LCD_WriteData(0x22); //
OSC
= 
10MHz
(hardware),// Parameter 1 changed from 0x23 to 0x22 2014

LCD_WriteData(0x02); //Parameter 2 Divider 
M
= 
2
, 
PLL
= 
360
/(M+1) = 120MHz

LCD_WriteData(0x54); //Parameter 3 Validate M and N values

Delay_ms(5);




// LCD_WriteIndex(0xE6); // SET PCLK 
freq
=
6
.5MHz/19MHz, pixel clk freq added2014

// LCD_WriteData(0x00);

// LCD_WriteData(0xEA);

// LCD_WriteData(0xEC);


//Set horizontal period

LCD_WriteIndex(SSD1963_SET_HORI_PERIOD);

LCD_WriteData((LCD_HT-1)>>8); //Set HT

LCD_WriteData(LCD_HT-1);

LCD_WriteData((LCD_HPS-1)>>8); //Set HPS

LCD_WriteData(LCD_HPS-1);

LCD_WriteData(DISP_HOR_PULSE_WIDTH-1); //Set HPW

LCD_WriteData(0x00);

LCD_WriteData(0x00);

LCD_WriteData(0x00);

Delay_ms(5);


//Set vertical period

LCD_WriteIndex(SSD1963_SET_VERT_PERIOD);

LCD_WriteData((LCD_VT-1)>>8); //Set VT

LCD_WriteData(LCD_VT-1);

LCD_WriteData((LCD_VPS-1)>>8); //Set VPS

LCD_WriteData(LCD_VPS-1);

LCD_WriteData(DISP_VER_PULSE_WIDTH-1); //Set VPW

LCD_WriteData(0x00); //Set FPS

LCD_WriteData(0x00);

Delay_ms(5);


//Set LSHIFT freq, i.e. the DCLK with PLL freq 120MHz set previously

//To obtain PCLK = 5.3MHz with PLL Frequency = 120MHz,

//5.3MHz = 120MHz * LCDC_FPR / 2^20

//LCDC_FPR = 46312


LCD_WriteIndex(SSD1963_SET_LSHIFT_FREQ);

LCD_WriteData(0x00); //changed from 0x01 to 0x00 according to Display Datasheet 2014

LCD_WriteData(0xB4); //changed from 0x33 to 0xB4 according to Display Datasheet 2014

LCD_WriteData(0xE7); //changed from 0x32 to 0xE7 according to Display Datasheet 2014

Delay_ms(5);


LCD_WriteIndex(SSD1963_SET_PIXEL_FORMAT); //Set pixel format, i.e. the bpp 

LCD_WriteData(0x50); // set 16bpp --> 101

Delay_ms(5);


LCD_WriteIndex(SSD1963_SET_PIXEL_DATA_INTERFACE); // Set pixel data interface 

LCD_WriteData(SSD1963_PDI_16BIT565); //16-bit(565 format) data for 16bpp


Delay_ms(5);


LCD_WriteIndex(SSD1963_ENTER_NORMAL_MODE); // SET normal mode added 2014


LCD_WriteIndex(SSD1963_SET_ADDRESS_MODE); //added 2014

LCD_WriteData(0x02); //changed from 2 to 0x02 2014 correct orientation

//see SSD1936 datasheet figure 9-12 to 9-15


LCD_WriteIndex(SSD1963_EXIT_INVERT_MODE); //added 2014


LCD_WriteIndex(SSD1963_SET_COLUMN_ADDRESS); // Set column address added 2014

LCD_WriteData(0x00); //SET start column address=0

LCD_WriteData(0x00);

LCD_WriteData(0x03); //SET end column address=800

LCD_WriteData(0x1F);


LCD_WriteIndex(SSD1963_SET_PAGE_ADDRESS); //SET page address added 2014

LCD_WriteData(0x00); //SET start page address=0

LCD_WriteData(0x00);

LCD_WriteData(0x01); //SET end page address=480

LCD_WriteData(0xDF);


LCD_WriteIndex(SSD1963_SET_SCROLL_AREA); //SET scroll area added 2014

LCD_WriteData(0x00);

LCD_WriteData(0x00);

LCD_WriteData((DISP_VER_RESOLUTION)>>8); //Set VerticalScrollArea

LCD_WriteData(DISP_VER_RESOLUTION);

LCD_WriteData(0x00);

LCD_WriteData(0x00);


LCD_WriteIndex(SSD1963_SET_SCROLL_START); //SET scroll start added 2014

LCD_WriteData(0x00); //Set VerticalScrollPointer

LCD_WriteData(0x00);


LCD_WriteIndex(SSD1963_EXIT_IDLE_MODE); //full color depth added 2014


LCD_WriteIndex(SSD1963_SET_DISPLAY_ON); // Turn on display


LCD_WriteIndex(SSD1963_WRITE_MEMORY_CONTINUE); //added 2014


//Delay_ms(5);  

}

Maybe somebody can see where the problem is causing the color malfunction. I attached the Display datasheet and the SSD1963 manual. ________________ Attachments : AT070TN92_V.1-Datasheet.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HzdK&d=%2Fa%2F0X0000000bQ2%2FuNd2XINSfsAK8F8jEnneUkjNY78_VMCC8iT9PNKRjqI&asPdf=falseSSD1963.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hzp5&d=%2Fa%2F0X0000000bQ3%2FKABI3u1PLs80StLjr5IVC3DmBvAtyCxRZSTHd7MsrLU&asPdf=false