Posted on January 31, 2018 at 09:21
Hello, that's the SRAM of STM32H7x3 microcontroller. I need to receive over 800 kib of data on high speed and place it in RAM via DMA. I read that there's 864 kib of ram here but I was confused to find out that it's segmented like that for some reason. My questions are:
1. What is AXI SRAM and how it's different from SRAM1-SRAM4? In linker configuration file it's used only for HEAP, but I want to declare an array here.
2. In DMA you assign starting address, amount of data and peripheral increment. Is there a way to receive 800 kib of consecutive data that way? The biggest region is 512 kib and it seems that some 'jumps' between the SRAMs are needed to be performed for it to work in the middle of DMA? I worked only with F4 dma, so maybe in H7 there's something different that could allow that?
Thank you!
